CCS/F28M35H52C: Code security module configuration of control sub system.

Hi,

This file is purely for the peripheral registers.

It has each peripheral register like CSM ( CSM register structure stored in the data section file CsmPwlFile)  mapped to the memory section ( CSM_PWL).

The structure can be found in *_sysctl.c.

This can be used to secure the memory as well as unlock the memory once the password is programmed using the asm file.

The ASM file you are referring to can be found in the common/source/* csmpassword.

The section where this password is stored .csm* will program the intended password.

This section will then have to be added to the device cmd file found at common/headers if not done already to map it to the intended memory.

Regards.

Hi Meghana,

Thank you for your reply. I was busy with another problem, so just got back into this issue.  So for me to lock the device i would need to add common/source/* csmpassword.asm which has

      .sect "csmpasswds"

      .long    0xFFFFFFFF        ;PWL0
      .long    0xFFFFFFFF        ;PWL1
      .long    0xFFFFFFFF        ;PWL2
      .long    0xFFFFFFFF        ;PWL3 (MSW of 128-bit password)
      
      .sect "ecslpasswds"
      
      .long 0xFFFFFFFF        ;ECSL0
      .long 0xFFFFFFFF        ;ECSL1
      
      .sect "flashexeonly"
      
      .long    0xFFFFFFFF        ;Flash Execute Only

Then in the device linker command file add these lines under SECTIONS

csmpasswds : > CSM_PWL PAGE = 1
ecslpasswds : > ECSL_PWL PAGE = 1
flashexeonly : > FLASH_EXE_ONLY PAGE = 1

where CSM_PWL,ECSL_PWL and FLASH_EXE_ONLY are defined in F28M3Xx_Headers_nonBIOS.cmd file ?

hi ,

Yes that right . The asm file would program the respective dedicated flash sectors with the password and the cmd file would map the section.

The CSM_PWL,ECSL_PWL and FLASH_EXE_ONLY need not be defined in F28M3Xx_Headers_nonBIOS.cmd file.
They can be done in the device cmd file found in common/cmd too.

Regards.

Hi,

I tried to do as above today. But as a precaution i changed the memory locations of CSM_PWL,ECSL_PWL and FLASH_EXE_ONLY in F28M3Xx_Headers_nonBIOS.cmd file to some shared RAM locations with same lengths. Then while building the project i get errors that assigned memory locations are not large enough for the variable stored there. So out of curiosity i just doubled the length of the memory sections in the .cmd file. Then the project builds successfully and in a debug session i checked the memory locations i assigned using memory browser. To me it looks like two variables are stored in the sections. For example in CSM_PWL sections there are 128 bits that are 0 and another 128 bits with the password that i assigned in the csmpassword.asm file.

What is the issue here? Please help.

Hi Meghana,

I used the following cmd files.

/*
//###########################################################################
// FILE:    F28M3Xx_Headers_nonBIOS.cmd
// TITLE:   F28M3Xx Peripheral registers linker command file
// DESCRIPTION:
//          This file is for use in Non-BIOS applications.
//          Linker command file to place the peripheral structures
//          used within the F28M3Xx headerfiles into the correct memory
//          mapped locations.
//          This version of the file includes the PieVectorTable structure.
//          For BIOS applications, please use the F28M3Xx_Headers_BIOS.cmd file
//          which does not include the PieVectorTable structure.
//###########################################################################
// $TI Release: F28M35x Support Library v220 $
// $Release Date: Tue Sep 26 15:35:11 CDT 2017 $
// $Copyright: Copyright (C) 2011-2017 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
*/

MEMORY
{
 PAGE 0:    /* Program Memory */

 PAGE 1:    /* Data Memory */

   DEV_EMU             : origin = 0x000880, length = 0x000180     /* device emulation registers */
   CSM                 : origin = 0x000AE0, length = 0x000020       /* code security module registers */

   ADC1_RESULT         : origin = 0x000B00, length = 0x000020     /* ADC1 Results register */
   ADC2_RESULT         : origin = 0x000B40, length = 0x000020     /* ADC2 Results register */

   CPU_TIMER0          : origin = 0x000C00, length = 0x000008     /* CPU Timer0 registers */
   CPU_TIMER1          : origin = 0x000C08, length = 0x000008     /* CPU Timer1 registers */
   CPU_TIMER2          : origin = 0x000C10, length = 0x000008     /* CPU Timer2 registers */

   PIE_CTRL            : origin = 0x000CE0, length = 0x000020     /* PIE control registers */
   PIE_VECT            : origin = 0x000D00, length = 0x000100     /* PIE Vector Table */
   PIE_VECT_CP         : origin = 0x000E00, length = 0x000100     /* PIE Vector Table Copy */

   DMA                 : origin = 0x001000, length = 0x000200     /* DMA registers */

   ASYSCTRLCONFIG      : origin = 0x001700, length = 0x000080       /* Analog System Control Configuration Registers */
 
   FLASH_REGS          : origin = 0x004000, length = 0x000300     /* Flash Control registers */
   FLASH_ECC           : origin = 0x004300, length = 0x000040     /* Flash/OTP ECC Error Log registers */

   M3PLL               : origin = 0x004400, length = 0x000010       /* M3 PLL Clock Configuration Registers  */

   EPI_REGS            : origin = 0x004430, length = 0x000010       /* EPI Registers  */
   
   RAM_REGS            : origin = 0x004900, length = 0x000080     /* RAM Control registers */
   RAM_ERR_REGS        : origin = 0x004A00, length = 0x000080     /* RAM ECC/PARITY/ACCESS Error Log Registers */

   CM_MC_IPC           : origin = 0x004E00, length = 0x000040     /* C28 Control to Master IPC registers */
       
   MCBSPA              : origin = 0x005000, length = 0x000040     /* McBSP-A registers */
   
   EPWM1               : origin = 0x005100, length = 0x000080     /* EPWM1 + HRPWM registers */
   EPWM2               : origin = 0x005180, length = 0x000080     /* EPWM2 + HRPWM registers */
   EPWM3               : origin = 0x005200, length = 0x000080     /* EPWM3 + HRPWM registers */
   EPWM4               : origin = 0x005280, length = 0x000080     /* EPWM4 + HRPWM registers */
   EPWM5               : origin = 0x005300, length = 0x000080     /* EPWM5 + HRPWM registers */
   EPWM6               : origin = 0x005380, length = 0x000080     /* EPWM6 + HRPWM registers */
   EPWM7               : origin = 0x005400, length = 0x000080     /* EPWM7 + HRPWM registers */
   EPWM8               : origin = 0x005480, length = 0x000080     /* EPWM8 + HRPWM registers */
   EPWM9               : origin = 0x005500, length = 0x000080     /* EPWM9 registers (no HRPWM) */

   ECAP1               : origin = 0x005A00, length = 0x000020     /* Enhanced Capture 1 registers */
   ECAP2               : origin = 0x005A20, length = 0x000020     /* Enhanced Capture 2 registers */
   ECAP3               : origin = 0x005A40, length = 0x000020     /* Enhanced Capture 3 registers */
   ECAP4               : origin = 0x005A60, length = 0x000020     /* Enhanced Capture 4 registers */
   ECAP5               : origin = 0x005A80, length = 0x000020     /* Enhanced Capture 5 registers */
   ECAP6               : origin = 0x005AA0, length = 0x000020     /* Enhanced Capture 6 registers */

   EQEP1               : origin = 0x005B00, length = 0x000040     /* Enhanced QEP 1 registers */
   EQEP2               : origin = 0x005B40, length = 0x000040     /* Enhanced QEP 2 registers */
   EQEP3               : origin = 0x005B80, length = 0x000040     /* Enhanced QEP 3 registers */

   GPIOG1CTRL          : origin = 0x005F80, length = 0x000040     /* GPIO control registers */
   GPIOG1DAT           : origin = 0x005FC0, length = 0x000020     /* GPIO data registers */
   GPIOG1TRIP          : origin = 0x005FE0, length = 0x000020     /* GPIO trip/LPM registers */

   COMP1               : origin = 0x006400, length = 0x000020     /* Comparator + DAC 1 registers */
   COMP2               : origin = 0x006420, length = 0x000020     /* Comparator + DAC 2 registers */
   COMP3               : origin = 0x006440, length = 0x000020     /* Comparator + DAC 3 registers */
   COMP4               : origin = 0x006460, length = 0x000020     /* Comparator + DAC 4 registers */
   COMP5               : origin = 0x006480, length = 0x000020     /* Comparator + DAC 5 registers */
   COMP6               : origin = 0x0064A0, length = 0x000020     /* Comparator + DAC 6 registers */

   GPIOG2CTRL          : origin = 0x006F80, length = 0x000040     /* GPIO control registers */
   GPIOG2DAT           : origin = 0x006FC0, length = 0x000020     /* GPIO data registers */
   
   SYSTEM              : origin = 0x007010, length = 0x000020     /* System control registers */

   SPIA                : origin = 0x007040, length = 0x000010     /* SPI-A registers */
   SCIA                : origin = 0x007050, length = 0x000010     /* SCI-A registers */

   NMIINTRUPT          : origin = 0x007060, length = 0x000010     /* NMI Watchdog Interrupt Registers */
   XINTRUPT            : origin = 0x007070, length = 0x000010     /* external interrupt registers */

   ADC1                : origin = 0x007100, length = 0x000080     /* ADC1 registers */
   ADC2                : origin = 0x007180, length = 0x000080     /* ADC2 registers */

   I2CA                : origin = 0x007900, length = 0x000040     /* I2C-A registers */

//   FLASH_EXE_ONLY      : origin = 0x13FFF2, length = 0x000002       /* FLASH execution only locations */
// ECSL_PWL            : origin = 0x13FFF4, length = 0x000004       /* FLASH ECSL password locations  */
//   CSM_PWL             : origin = 0x13FFF8, length = 0x000008     /* FLASH CSM password locations.  */

     FLASH_EXE_ONLY      : origin = 0x000400, length = 0x000002       /* FLASH execution only locations */
     ECSL_PWL            : origin = 0x000402, length = 0x000004       /* FLASH ECSL password locations  */
     CSM_PWL             : origin = 0x000406 length = 0x000008     /* FLASH CSM password locations.  */
}


SECTIONS
{
/*** PIE Vect Table and Boot ROM Variables Structures ***/
  UNION run = PIE_VECT, PAGE = 1
   {
      PieVectTableFile
      GROUP
      {
         EmuKeyVar
         EmuBModeVar
         FlashCallbackVar
         FlashScalingVar
      }
   }

/*** Peripheral Frame 0 Register Structures ***/
   DevEmuRegsFile       : > DEV_EMU,     PAGE = 1
   CsmRegsFile          : > CSM,         PAGE = 1
   UNION run =              ADC1_RESULT, PAGE = 1
   {
       AdcResultFile
       Adc1ResultFile
   }
   Adc2ResultFile        : > ADC2_RESULT,     PAGE = 1
   CpuTimer0RegsFile     : > CPU_TIMER0,      PAGE = 1
   CpuTimer1RegsFile     : > CPU_TIMER1,      PAGE = 1
   CpuTimer2RegsFile     : > CPU_TIMER2,      PAGE = 1
   PieCtrlRegsFile       : > PIE_CTRL,        PAGE = 1
   PieVectTableCopyFile  : > PIE_VECT_CP,     PAGE = 1
   DmaRegsFile           : > DMA,             PAGE = 1     
   AnalogSysctrlRegsFile : > ASYSCTRLCONFIG,  PAGE = 1

/*** Peripheral Frame 1 Register Structures ***/
   FlashCtrlRegsFile : > FLASH_REGS,  PAGE = 1
   FlashEccRegsFile  : > FLASH_ECC,   PAGE = 1
   M3PllRegsFile     : > M3PLL,       PAGE = 1
   EpiRegsFile       : > EPI_REGS     PAGE = 1
   RAMRegsFile       : > RAM_REGS,    PAGE = 1
   RAMErrRegsFile    : > RAM_ERR_REGS,PAGE = 1
   CtoMIpcRegsFile   : > CM_MC_IPC,   PAGE = 1
   
/*** Peripheral Frame 2 Register Structures ***/
   SysCtrlRegsFile   : > SYSTEM,      PAGE = 1
   SpiaRegsFile      : > SPIA,        PAGE = 1
   SciaRegsFile      : > SCIA,        PAGE = 1
   NmiIntruptRegsFile: > NMIINTRUPT,  PAGE = 1
   XIntruptRegsFile  : > XINTRUPT,    PAGE = 1
   UNION run =           ADC1,        PAGE = 1
   {
       AdcRegsFile
       Adc1RegsFile
   }
   Adc2RegsFile      : > ADC2,        PAGE = 1
   I2caRegsFile      : > I2CA,        PAGE = 1

/*** Peripheral Frame 3 Register Structures ***/
   McbspaRegsFile    : > MCBSPA,      PAGE = 1
   EPwm1RegsFile     : > EPWM1,       PAGE = 1
   EPwm2RegsFile     : > EPWM2,       PAGE = 1
   EPwm3RegsFile     : > EPWM3,       PAGE = 1
   EPwm4RegsFile     : > EPWM4,       PAGE = 1
   EPwm5RegsFile     : > EPWM5,       PAGE = 1
   EPwm6RegsFile     : > EPWM6,       PAGE = 1
   EPwm7RegsFile     : > EPWM7,       PAGE = 1
   EPwm8RegsFile     : > EPWM8,       PAGE = 1
   EPwm9RegsFile     : > EPWM9,       PAGE = 1
   ECap1RegsFile     : > ECAP1,       PAGE = 1
   ECap2RegsFile     : > ECAP2,       PAGE = 1
   ECap3RegsFile     : > ECAP3,       PAGE = 1
   ECap4RegsFile     : > ECAP4,       PAGE = 1
   ECap5RegsFile     : > ECAP5,       PAGE = 1
   ECap6RegsFile     : > ECAP6,       PAGE = 1
   EQep1RegsFile     : > EQEP1,       PAGE = 1   
   EQep2RegsFile     : > EQEP2,       PAGE = 1               
   EQep3RegsFile     : > EQEP3,       PAGE = 1               
   UNION run =           GPIOG1CTRL,  PAGE = 1
   {
       GpioCtrlRegsFile
       GpioG1CtrlRegsFile
   }
   UNION run =           GPIOG1DAT,  PAGE = 1
   {
       GpioDataRegsFile
       GpioG1DataRegsFile
   }
   UNION run =           GPIOG1TRIP,  PAGE = 1
   {
       GpioTripRegsFile
       GpioG1TripRegsFile
   }

   Comp1RegsFile      : > COMP1,       PAGE = 1
   Comp2RegsFile      : > COMP2,       PAGE = 1
   Comp3RegsFile      : > COMP3,       PAGE = 1
   Comp4RegsFile      : > COMP4,       PAGE = 1
   Comp5RegsFile      : > COMP5,       PAGE = 1
   Comp6RegsFile      : > COMP6,       PAGE = 1
   GpioG2CtrlRegsFile : > GPIOG2CTRL,  PAGE = 1
   GpioG2DataRegsFile : > GPIOG2DAT,   PAGE = 1
   
/*** Code Security Module Register Structures ***/
   FlashExeOnlyFile  : > FLASH_EXE_ONLY,      PAGE = 1
   EcslPwlFile       : > ECSL_PWL,            PAGE = 1
   CsmPwlFile        : > CSM_PWL,             PAGE = 1
}

/*
*/

/*
//###########################################################################
// FILE:    28M35M52C1_RAM_lnk_c28.cmd
// TITLE:   Linker Command File for F28M35M52C1 examples that run out of RAM
//          This ONLY includes all SARAM blocks on the F28M35M52C1 device.
//          This does not include flash or OTP.
//          Keep in mind that L0 and L1 are protected by the code
//          security module.
//          What this means is in most cases you will want to move to
//          another memory map file which has more memory defined.
//###########################################################################
// $TI Release: F28M35x Support Library v220 $
// $Release Date: Tue Sep 26 15:35:11 CDT 2017 $
// $Copyright: Copyright (C) 2011-2017 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
*/

/* ======================================================
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
// The header linker files are found in <base>\F28M35x_headers\cmd
// For BIOS applications add:      F28M35x_Headers_BIOS.cmd
// For nonBIOS applications add:   F28M35x_Headers_nonBIOS.cmd
========================================================= */

/* Define the memory block start/length for the F28M35x
   PAGE 0 will be used to organize program sections
   PAGE 1 will be used to organize data sections

   Notes:
         Memory blocks on F28M35x are uniform (ie same
         physical memory) in both PAGE 0 and PAGE 1.
         That is the same memory region should not be
         defined for both PAGE 0 and PAGE 1.
         Doing so will result in corruption of program
         and/or data.

         Contiguous SARAM memory blocks can be combined
         if required to create a larger memory block.
*/

MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */

   BEGIN       : origin = 0x000000, length = 0x000002
   RAMM0       : origin = 0x0001A2, length = 0x00025E     /* on-chip RAM block M0 */
   RAML0L1     : origin = 0x008000, length = 0x002000     /* on-chip RAM block L0, L1 */   
    
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* Part of Boot ROM */
   FPUTABLES   : origin = 0x3FD258, length = 0x0006A0      /* FPU Tables in Boot ROM */
   IQTABLES    : origin = 0x3FD8F8, length = 0x000B50     /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FE448, length = 0x00008C     /* IQ Math Tables in Boot ROM */
   IQTABLES3   : origin = 0x3FE4D4, length = 0x0000AA      /* IQ Math Tables in Boot ROM */

   BOOTROM     : origin = 0x3FEDA8, length = 0x001200     /* Boot ROM */


PAGE 1 :

   BOOT_RSVD   : origin = 0x000002, length = 0x0001A0     /* Part of M0, BOOT rom will use this for stack */
   //RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAML2L3       : origin = 0x00A000, length = 0x002000      /* on-chip RAM block L2 */
 //  RAML3       : origin = 0x00B000, length = 0x001000     /* on-chip RAM block L3 */
   RAMS0       : origin = 0x00C000, length = 0x001000     /* on-chip Shared RAM block S0 */
   RAMS1       : origin = 0x00D000, length = 0x001000     /* on-chip Shared RAM block S1 */
   RAMS2       : origin = 0x00E000, length = 0x001000     /* on-chip Shared RAM block S2 */
   RAMS3       : origin = 0x00F000, length = 0x001000     /* on-chip Shared RAM block S3 */
   RAMS4       : origin = 0x010000, length = 0x001000     /* on-chip Shared RAM block S4 */
   RAMS5       : origin = 0x011000, length = 0x001000     /* on-chip Shared RAM block S5 */
   RAMS6       : origin = 0x012000, length = 0x001000     /* on-chip Shared RAM block S6 */
   RAMS7       : origin = 0x013000, length = 0x001000     /* on-chip Shared RAM block S7 */

   CTOMRAM     : origin = 0x03F800, length = 0x000380     /* C28 to M3 Message RAM */
   MTOCRAM     : origin = 0x03FC00, length = 0x000380     /* M3 to C28 Message RAM */
}


SECTIONS
{
   /* Setup for "boot to SARAM" mode:
      The codestart section (found in DSP28_CodeStartBranch.asm)
      re-directs execution to the start of user code.  */
   codestart        : > BEGIN,      PAGE = 0
   .text            : > RAML2L3,    PAGE = 1
   .cinit           : > RAML2L3,      PAGE = 1
   .pinit           : > RAMS0,      PAGE = 1
   .switch          : > RAMS0,      PAGE = 1
   .reset           : > RESET,      PAGE = 0, TYPE = DSECT /* not used, */

   .stack           : > RAMM0,      PAGE = 0
   .ebss            : > RAMS0,      PAGE = 1
   .econst          : > RAML2L3,      PAGE = 1
   .esysmem         : > RAML2L3,      PAGE = 1

   IQmath           : > RAMS0,    PAGE = 1
   IQmathTables     : > IQTABLES,   PAGE = 0, TYPE = NOLOAD

    ramfuncs         : >  RAMS0,      PAGE = 1
   

   CtoM_MsgRAM            : > RAMS6 PAGE=1
   MtoC_MsgRAM            : > RAMS7 PAGE=1
   /* The following section definitions are required when using the IPC API Drivers */
   GROUP : > CTOMRAM, PAGE = 1
   {
       PUTBUFFER
       PUTWRITEIDX
       GETREADIDX
   }

   GROUP : > MTOCRAM, PAGE = 1
   {
       GETBUFFER :    TYPE = DSECT
       GETWRITEIDX :  TYPE = DSECT
       PUTREADIDX :   TYPE = DSECT
   }  
   
   /* Allocate FPU math areas: */
   FPUmathTables    : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD

 /*  DMARAML2            : > RAML2,        PAGE = 1
   DMARAML3            : > RAML3,        PAGE = 1
   DMARAMS0            : > RAMS0,        PAGE = 1
   DMARAMS1            : > RAMS1,        PAGE = 1
   DMARAMS2            : > RAMS2,        PAGE = 1
   DMARAMS3            : > RAMS3,        PAGE = 1
   DMARAMS4            : > RAMS4,        PAGE = 1
   DMARAMS5            : > RAMS5,        PAGE = 1
   DMARAMS6            : > RAMS6,        PAGE = 1
   DMARAMS7            : > RAMS7,        PAGE = 1   
*/

   SHARERAMS2          : > RAMS2,        PAGE = 1
   SHARERAMS3          : > RAMS3,        PAGE = 1
   SHARERAMS4          : > RAMS4,        PAGE = 1


  /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables2    : > IQTABLES2,  PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)

   }
   */
   /* Uncomment the section below if calling the IQNasin() or IQasin()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables3    : > IQTABLES3,  PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)

   }
   */

   csmpasswds :> CSM_PWL, PAGE =1
   ecslpasswds :> ECSL_PWL, PAGE=1
   flashexeonly :> FLASH_EXE_ONLY, PAGE=1

}

I have changed the memory allocations for CSM_PWL,ECSL_PWL and FLASH_EXE_ONLY to Ram locations which used to be RAMM1. I have comment out that allocation in 28M35M52C1_RAM_lnk_c28.cmd file.

when i try to buid this code, I get following error for all three memory sections

#10099-D</a>  program will not fit into available memory.  placement with alignment/blocking fails for section "csmpasswds" size 0x8 page 1.  Available memory ranges:

So i did following changes to the F28M3Xx_Headers_nonBIOS.cmd file

FLASH_EXE_ONLY      : origin = 0x000400, length = 0x000004       /* FLASH execution only locations */
ECSL_PWL            : origin = 0x000404, length = 0x000008       /* FLASH ECSL password locations  */
CSM_PWL             : origin = 0x000412 length = 0x000016     /* FLASH CSM password locations.  */

Then the code compiles and when i chekc the memory sections in a debug session i get the following,

I think there are two variable stored in each of the above sections?

Part Number: F28M35H52C

Tool/software: Code Composer Studio

Hi,

As i have asked in the previous question, I have yet been unable to find a solution to my problem. When i tried code security module configurations on different RAM locations, the variables are not written correctly. I haven't tried this on the actual code security module memory locations as i think may lock the device permanently. Please help.

Hareesh,

After adding F28M35x_CSMPasswords.asm file to the project, i should add following lines to the project linker command file, right?

csmpasswds :> CSM_PWL, PAGE =1
ecslpasswds :> ECSL_PWL, PAGE=1
flashexeonly :> FLASH_EXE_ONLY, PAGE=1

Because one of my predecessors has permanently locked the device,i wanted to test it first. That's why i edited following lines in F28M3Xx_Headers_nonBIOS.cmd to RAMM1 location. (I have edited the RAMM1 length to suite this in project linker command file.)

 FLASH_EXE_ONLY      : origin = 0x000400, length = 0x000002       /* FLASH execution only locations */
 ECSL_PWL            : origin = 0x000404, length = 0x000004       /* FLASH ECSL password locations  */
 CSM_PWL             : origin = 0x000412 length = 0x00008     /* FLASH CSM password locations.  */

This does not work, gives 3 errors like,

#10099-D</a>  program will not fit into available memory.  placement with alignment/blocking fails for section "csmpasswds" size 0x8 page 1.

Have no idea why it does not work.

Chinthaka,

            As explained in my previous post, there is no need to edit any linker command file. F28M35H52C1_c28.cmd has all the sections/assignments correctly defined. Simply add that file to your project. It is likely you are using 28M35H52C1_RAM_lnk_c28.cmd right now and running your project off RAM. Using CSM implies you are running the project off flash, so you need to switch the linker command file. You are attempting to load the passwords to RAM, which is not a useful exercise.

As already explained in my previous post, “the device is not locked until PASSWDLOCK field of the OTPSECLOCK register is written with a value other than “0x1111” to secure the device.” This should prevent any accidental locking.

Thanks. I will give it a try and get back to you.

Hi Hareesh,

Like you advised i used the  \controlSUITE\device_support\f28m35x\v220\F28M35x_common\cmd\F28M35H52C1_c28.cmd file and just included the F28M35x_CSMPasswords.asm file. It resulted in following error.

#10099-D</a>  program will not fit into available memory.  placement with alignment/blocking fails for section "flashexeonly" size 0x2 page 0.

Originally length of FLASH_EXE_ONLY_P0 is 2. How can i get this fixed?

Jayarathne,

You need to go though linker cmd file usage on C28x to understand it better. It is difficult to point to the issue based on description you have provided. You can refer below link and see if this provides info to debug the issue.

Regards,

Vivek Singh