For a given device/HRPWM instance, at fixed voltage and fixed temperature, what is a rough ballpark for typical HRPWM MEP step size variance? Using SFO, we will have an average step size, represented as a number of steps per one sysclk tick. Understand that this is not a characterized data manual parameter, just trying to get a rough understanding of what to expect, i.e. +/- 10%, 20%, 40%? The use case is understanding the absolute delay of say 5 to 10 steps. If the average value is used, what would be a decent rule of thumb for the error (using SFO based average)?
A side question would be related to voltage sensitivity. Can a change from 1.2 to 1.15V have a significant impact? This relates to the assumption of fixed voltage.