CCS/TMS320F28035: Configure RAM memory of TMS320F28035

Sebastián,

I recommend you download the latest version of C2000Ware, which contains a set of examples for this device. There is an example which sets up an ISR to read the ADC and log results into a small array. If you install in the default directory, you will find this at:
C:\ti\c2000\C2000Ware_1_00_06_00\device_support\f2803x\examples\c28\adc_soc

I think this will do everything you need. Post back if it's not what you were looking for.

Regards,

Richard

Hi Richard 

I´m reviewing the code example "Example_2803xAdcSoc". Using this example, I define a table, define an index and include this in my program. So, I compile my program and proceed a debug session. When I execute my program step by step, in the section where I use the table of ram, only two times enter to this section, because don´t comeback the program counter to the breakpoint anymore. Therefore, that procedure doesn´t useful to me. I only need acces controlled to ram memory.

I hope that someone can aid to me.

Thankyou very much.

Sebastián...

Hi Sebastián,

I can't say what's wrong without seeing the code.  Could you zip the project and attach it to a post so I can look through the code please?

Thanks.

Regards,

Richard

Hi Richard

I send a word file where I show screenviews and explain the changes that I made. Furthermore I send my project Lab7 in zip format.

Thanks a lot.

Sebastián

information to TI.docx

 

7522.Lab7.zip

Hi Sebastián,

It appears you have taken files from Lab7 of the 3-day F28035 workshop and added code from the ADC SOC example in the header files. Nothing wrong in principle with doing that, but a couple of things look wrong to me.

The ISR you pasted into the Word document is triggered by EPWM1. When the ISR begins you correctly write to the PIEACK register, but I do not see where the peripheral interrupt flag is being cleared. You would normally be writing to ETCLR.INT to clear that. Not doing so will mean your should only get the first interrupt. You'll need to add this to the PWM ISR:

EPwm1Regs.ETCLR.bit.INT = 1;

I don't follow what the code in that ISR is doing. You seem to be forcing an ADC SOC in software, then immediately reading the result register, which will hold the result of the previous conversion. You seem to have disabled the ADC ISR, but a cleaner way of handling this would be to forget about the PWM ISR and work within the ADC ISR. That way you'll know fresh results are available when you read them. You could then write the desired duty cycle into the PWM shadow duty cycle registers.

Regards,

Richard