TMS320F280049C: how to prevent RAM content change after flash programming?

Hi,

FLASH plug-in loads the API  into RAM hence yes, it'll change the RAM content. I am still not understanding the issue though. Any code in RAM should get loaded from flash at run time so this really should not be issue. Can you explain a bit more about the issue?

Regards,

Vivek Singh

Hi again

I use the dsp for controlling an inverter.I use the Flash for program. when the inverter starts switching and supplying the load,because of noise, the JTAG programmer gets disconnected and I don't have access to variables during inverter run. In 288335 and 28069 DSPs, in order to have log of some variables such as voltages, currents, voltage references, etc, I defined a GPIO for an external key for Log Enable. when it is enable, the variables are stored in an array in RAM and when it is disabled, the array update is disabled and the array retained the last values. after stopping the inverter and connecting again to the DSP, because the RAM contents where unchanged, I could see the last arrays of voltages and currents and plot for example, the last 20ms of voltages before the inverter is turned off. 

Now I am using 280049 and I need the same feature to debug my control loops and ....

This is an example:(first I make Inv_On = 1 by an external key, then turn on the inverter(JTAG disconnects at this time), then make Inv_On = 0 by the external key, then turn off the inverter, then connect JTAG to DSP again by programming the flash, then I plot the dtlog1 and dtlog2 which are arrays of length 800.

//global variables

int   dtlog1[800],dtlog2[800];

mainISR()

{

if(Inv_On == 1)

{

dtlog1[Datalogptr] = SpeedRef;
dtlog2[Datalogptr] = SpeedFeedback ;

Datalogptr = (Datalogptr + 1) % 800;

}

}

In 280049, when I use LS RAMs for dtlog1 and dtlog2 arrays, they become zero after flash programing. and when I use GS RAMs, they have unknown nonzero values. Do you have any suggestion for the datalog?

Even when I don't use flash and use F280049_RAM_CPU.cmd and load and run the code from RAM, All the RAM including LS ,GS and M1 are reset to zero.

but according to the following post, you replied "On F280049 device, RAMs are not cleared by BOOTROM on XRSn."

https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/814870

Best regards,

In summary, I need a portion of RAM for Data Section which is not changed or reset to zero after flash programming. Is it possible?

but according to the following post, you replied "On F280049 device, RAMs are not cleared by BOOTROM on XRSn."

That is correct. On hardware, we don't have any issue with this. Even on WD reset, RAM content are not cleared. LS RAM should not get updated unless it is getting initialize in software. Can you disable the run to main feature in CCS and then see if you still seeing same issue.

Regards,

Vivek Singh

I had disabled run to main before. The problem is not due to it.

Does the variables get zero value  if they are not initialized?

for example

int xx; 

without assigning  any value to it, has initial value of zero? or gets it's RAM address content? I know in 28335 it gets it's RAM address content.

Following is the Linker Command File I use. maybe it could help. if I use RAMGS1_3 for .ebss, the uninitialized variables get unknown values after flash programming, which I think as you said is due to flash api running in RAM. if I use RAMLS2_3 , the uninitialized variables get zero value.

For your information, my code is based on instaspin projects and I use XDS100-V2 programmer.

MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to Flash" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
RESET : origin = 0x3FFFC0, length = 0x000002

patch_EST_Angle_run_patchable_address : origin = 0x009000, length = 0x00000e
patch_EST_Dir_run_patchable_address : origin = 0x00900e, length = 0x00000e
patch_EST_Eab_run_patchable_address : origin = 0x00901c, length = 0x00000e
patch_EST_Flux_ab_estFluxDot_patchable_address : origin = 0x00902a, length = 0x00000e
patch_EST_Flux_dq_run_patchable_address : origin = 0x009038, length = 0x00000e
patch_EST_Flux_run_patchable_address : origin = 0x009046, length = 0x00000e
patch_EST_Freq_run_patchable_address : origin = 0x009054, length = 0x00000e
patch_EST_Iab_run_patchable_address : origin = 0x009062, length = 0x00000e
patch_EST_Idq_run_patchable_address : origin = 0x009070, length = 0x00000e
patch_EST_Ls_run_patchable_address : origin = 0x00907e, length = 0x00000e
patch_EST_OneOverDcBus_run_patchable_address : origin = 0x00908c, length = 0x00000e
patch_EST_Rr_run_patchable_address : origin = 0x00909a, length = 0x00000e
patch_EST_RsOnLine_run_patchable_address : origin = 0x0090a8, length = 0x00000e
patch_EST_Rs_run_patchable_address : origin = 0x0090b6, length = 0x00000e
patch_EST_Vab_run_patchable_address : origin = 0x0090c4, length = 0x00000e
patch_EST_Vdq_run_patchable_address : origin = 0x0090d2, length = 0x00000e
patch_EST_runEst_patchable_address : origin = 0x0090e0, length = 0x00000e

RAMLS4_7 : origin = 0x00A000, length = 0x002000

FLASHB0_SA : origin = 0x080002, length = 0x00FFFE /* on-chip Flash */
FLASHB1_SA : origin = 0x090000, length = 0x010000 /* on-chip Flash */

PAGE 1 :
BOOT_RSVD : origin = 0x000002, length = 0x0000F3 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x0000F5, length = 0x00030B
RAMM1 : origin = 0x000400, length = 0x000400

/* CLA1 : origin = 0x001400, length = 0x000080 */ /* Defined in header cmd file */

RAMGS0_A : origin = 0x00C000, length = 0x002000
RAMGS1_3 : origin = 0x00E000, length = 0x006000

RAMLS0_1 : origin = 0x008000, length = 0x001000 /* Can't be used, reserved for FAST object */
RAMLS2_3 : origin = 0x009100, length = 0x000F00 /* */

CLA1MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1MSGRAMHIGH : origin = 0x001500, length = 0x000080

}

SECTIONS
{
.TI.ramfunc : LOAD = FLASHB0_SA,
RUN = RAMLS4_7,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)

codestart : > BEGIN, PAGE = 0, ALIGN(4)
.text : > FLASHB0_SA, PAGE = 0, ALIGN(4)
.cinit : > FLASHB0_SA, PAGE = 0, ALIGN(4)
.pinit : > FLASHB0_SA, PAGE = 0, ALIGN(4)
.switch : > FLASHB0_SA, PAGE = 0, ALIGN(4)
.econst : > FLASHB0_SA, PAGE = 0, ALIGN(4)

.reset : > RESET, PAGE = 0, TYPE = DSECT
.cio : > RAMLS4_7, PAGE = 0
.stack : > RAMM0, PAGE = 1
.ebss : > RAMLS2_3, PAGE = 1
.esysmem : > RAMGS0_A, PAGE = 1

/* Cla1RegsFile : > CLA1, PAGE = 1 */ /* Defined in header .cmd file*/

.bss_cla : > RAMGS1_3, PAGE = 1

Cla1Prog : > FLASHB0_SA,
RUN = RAMLS4_7,
LOAD_START(_Cla1ProgLoadStart),
RUN_START(_Cla1ProgRunStart),
LOAD_SIZE(_Cla1ProgLoadSize),
PAGE = 0, ALIGN(4)

Cla1Prog2 : > FLASHB0_SA,
RUN = RAMLS4_7,
LOAD_START(_Cla1Prog2LoadStart),
RUN_START(_Cla1Prog2RunStart),
LOAD_SIZE(_Cla1Prog2LoadSize),
PAGE = 0, ALIGN(4)

Cla1ToCpuMsgRAM : > CLA1MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1MSGRAMHIGH, PAGE = 1

.const_cla : > FLASHB0_SA,
RUN = RAMLS4_7,
RUN_START(_Cla1ConstRunStart),
LOAD_START(_Cla1ConstLoadStart),
LOAD_SIZE(_Cla1ConstLoadSize),
PAGE = 0

.scratchpad : > RAMGS1_3, PAGE = 1

patch_EST_Angle_run_patchable_section : > patch_EST_Angle_run_patchable_address, PAGE = 0
patch_EST_Dir_run_patchable_section : > patch_EST_Dir_run_patchable_address, PAGE = 0
patch_EST_Eab_run_patchable_section : > patch_EST_Eab_run_patchable_address, PAGE = 0
patch_EST_Flux_ab_estFluxDot_patchable_section : > patch_EST_Flux_ab_estFluxDot_patchable_address, PAGE = 0
patch_EST_Flux_dq_run_patchable_section : > patch_EST_Flux_dq_run_patchable_address, PAGE = 0
patch_EST_Flux_run_patchable_section : > patch_EST_Flux_run_patchable_address, PAGE = 0
patch_EST_Freq_run_patchable_section : > patch_EST_Freq_run_patchable_address, PAGE = 0
patch_EST_Iab_run_patchable_section : > patch_EST_Iab_run_patchable_address, PAGE = 0
patch_EST_Idq_run_patchable_section : > patch_EST_Idq_run_patchable_address, PAGE = 0
patch_EST_Ls_run_patchable_section : > patch_EST_Ls_run_patchable_address, PAGE = 0
patch_EST_OneOverDcBus_run_patchable_section : > patch_EST_OneOverDcBus_run_patchable_address, PAGE = 0
patch_EST_Rr_run_patchable_section : > patch_EST_Rr_run_patchable_address, PAGE = 0
patch_EST_RsOnLine_run_patchable_section : > patch_EST_RsOnLine_run_patchable_address, PAGE = 0
patch_EST_Rs_run_patchable_section : > patch_EST_Rs_run_patchable_address, PAGE = 0
patch_EST_Vab_run_patchable_section : > patch_EST_Vab_run_patchable_address, PAGE = 0
patch_EST_Vdq_run_patchable_section : > patch_EST_Vdq_run_patchable_address, PAGE = 0
patch_EST_runEst_patchable_section : > patch_EST_runEst_patchable_address, PAGE = 0
}

SECTIONS
{
sysctrl_data : > RAMM1 , PAGE = 1
ctrl_data : > RAMM1 , PAGE = 1
est_data : > RAMGS0_A, PAGE = 1

}

SECTIONS
{
datalog_data : > RAMGS0_A, PAGE = 1
graph_data : > RAMGS0_A, PAGE = 1
}

Do you have any suggestion?

Hi,

Does the variables get zero value  if they are not initialized?

for example

int xx; 

without assigning  any value to it, has initial value of zero? or gets it's RAM address content? I know in 28335 it gets it's RAM address content.

On this device all the RAMs are cleared to 0x0 after power on reset (only) hence unless any RAM location is not updated by application, the value will be 0x0 only.

Regards,

Vivek Singh

Does flash programming perform a POR that clears the RAM to 0x0?

No, it'll be only debug reset.