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TMS320F28379D: Stack Handling of the C28x

Ralf Bartling
Expert 1025 points
Part Number: TMS320F28379D

Hello,

I have a question regarding the stack handling of the C28x controller.

In the manual “TMS320C28x CPU and Instruction Set” on page 28 can be found:

When 32-bit operations read or write a 32-bit value, the C28x CPU expects the memory wrapper or peripheral-interface logic to align that read or write to an even address. For example, if the SP contains the odd address “0000 0083”, a 32-bit read operation reads from addresses “0000 0082” and 0000.

What does “memory wrapper or peripheral-interface logic” mean?

During an interrupt context save (chapter 3.4) the SP is automatically incremented by one. What happens if the SP points before to an even address? In this case the SP would contain an odd address before the registers are saved.

  • 0
    TI__Mastermind 27200 points

    The term "memory wrapper' refers to hardware addressing logic associated with the RAM block. "Peripheral interface logic" is hardware which controls data read/write operations between each peripheral or CPU and an internal memory bus. Whether these terms should be used in a reference guide is debatable. Both refer to internal hardware over which the programmer has no control.

    The last address stated in the same paragraph should be 0000 0083. I will file a literature bug for that. The main point is that if SP is odd aligned and a 32-bit write access is made, the write will take place to that odd word address and to the even word address below it on a little endian basis.

    Now thinking about this in relation to the interrupt auto context save sequence on p.60, if SP is even word aligned prior to the interrupt, incrementing SP by 1 will indeed make SP odd aligned, but a 32-bit write access will still take place over consecutive, even word aligned locations. All write accesses made during the auto context save are 32-bits, and incrementing SP by 1 ensures that data already on the stack is never over-written by the context save sequence. Table 3-4 shows the write sequence in both cases.

    Let me know if anything is still unclear and I'll be pleased to go over it again.

    BTW, I think you have a duplicate post on this issue which I will close. Thanks.

    Regards,

    Richard

  • 0 in reply to Richard Poley
    Expert 1025 points

    Dear Richard,

    many thanks for your information. I have now understand the handling of the SP during an interrupt context. Maybe there is another small error in the table 3.4 of the manual (see attachment).

    I have two other questions.

    I have worked with the TMS320F240 20 years ago. This DSP has three different memory areas (program, data and i/o) of 64kWords.

    Does the C28x also have separate memory areas or do we have one linear address range?

    The second question is regarding the PieVectTable. I´m just working on the one day workshop of the TMS320F28379D launchpad. In one of the examples (LAB2) the PieVectTable is loaded during runtime with the addresses of the interrupt service routines. In all examples of the workshop the program is loaded and executed from the RAM. Now I want to run the LAB2 example from the Flash memory.

    Is the PieVectTable part of the RAM or the flash memory area?

    If the PieVectTable would be part of the flash, it has to be programmed during the programming of the flash memory.

     

    Regards

    Ralf

    attachment.pdf

     

  • 0 in reply to Ralf Bartling
    TI__Mastermind 27200 points

    Dear Ralf,

    Thanks for pointing out the error in the literature. I will enter a bug against that for correction in the next revision of the document.

    On C28x there is no I/O space. There are program and data spaces, but the memory is unified, meaning that any block can be assigned to either program or data space. This is done in the linker command file. The memory map is linear, but not completely contiguous - see section 6.3 of the datasheet for details.

    The PIE vector table is located in a fixed memory range in RAM which is addressible in data space only. The table must be loaded prior to enabling interrupts whether the program is in RAM or flash. Though it doesn't cover this device, there is a good application report which may help here:
    http://www.ti.com/lit/an/spra958l/spra958l.pdf

    Hope this helps. Feel free to post back if anything's unclear.

    Regards,

    Richard