PWM State during Reset

I don't believe there is any flash location and/or register to define PWM output state on reset. However, all uni-supply devices ensure glitch free PWM output by making sure GPIOs becomes input during booting sequence and the level can be controlled by pull up or down. For dual supply devices also this is true as long as both core and IO supply comes up together. By the way, I believe 281x devices have to managed differently as far as initial IO state goes. Please check the datasheet of the device you are planning to evaluate.  Also, depending on the drive design (I am assuming you are referring to a drive application) .. one may not energize DC bus before the control board and in that case this issue will not be present.

When I reset the CPU after having run some PWM, switches go into some states (ON/OFF) which is not I want.

How and where can I define,, what the state of switches should be, upon reset.

Please explain in detail.

Thanks

Hi Shyam,

I do agree with Arefeen.

shyam nair said:

How and where can I define,, what the state of switches should be, upon reset.

ePWM peripheral initialization should take care of this where you can initialize CMPA value to min. or max. according to your requirement.

Regards,

Gautam

I mean initial peripheral configuration in main is what the user can do. For eg.

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
   EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD;       // Set timer period
   EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;    // Disable phase loading
   EPwm1Regs.TBPHS.half.TBPHS = 0x0000;       // Phase is 0
   EPwm1Regs.TBCTR = 0x0000;                  // Clear counter
   EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2;   // Clock ratio to SYSCLKOUT
   EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV2;

   // Setup shadow register load on ZERO
   EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
   EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

   // Set Compare values - Min CMPA Value
   EPwm1Regs.CMPA.half.CMPA = EPWM1_MIN_CMPA;    // Set compare A value
   EPwm1Regs.CMPB = EPWM1_MIN_CMPB;              // Set Compare B value

   // Set actions
   EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;            // Set PWM1A on Zero
   EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;          // Clear PWM1A on event A, up count

   EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET;            // Set PWM1B on Zero
   EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR;          // Clear PWM1B on event B, up count

Regards,

Gautam