HI
I am using quadrature encoder with A+A-, B+B-, Z+Z- output pins having 1000 lines/revolution. I think Z+Z- pins are for index output. I have checked that at every revolution this Z+Z- generate 5V pulse. Problem is that I want to reset position counter at every index signal. However index pin generates now effect for resetting the position counter or position counter latch. I am afraid may be i am wrong with this concept of index pin.
I am using following code:
void Init_eQEP1(void){
// Setup eQEP1 Decoder Control
EQep1Regs.QDECCTL.bit.QSRC = 00; // Quadrature count mode
EQep1Regs.QDECCTL.bit.SOEN = 1; // Enable position-compare sync output
EQep1Regs.QDECCTL.bit.SPSEL = 0; // Index pin will be used for synchronous signal
// Setup eQEP1 Unit Timer Period(1ms)
EQep1Regs.QUPRD = 150000; // SYSCLKOUT(=150MHz)/1000 = 1ms period
// Setup eQEP1 Position Counter Initialization
EQep1Regs.QPOSINIT = 0x00000000;
// Setup eQEP1 Maximum Position Counter
EQep1Regs.QPOSMAX = 3999;
// Setup eQEP1 Control
// Emulation Control Bits
// position counter, watchdog counter, unit timer, capture timer is unaffected by emulation suspend
EQep1Regs.QEPCTL.bit.FREE_SOFT = 2;
EQep1Regs.QEPCTL.bit.PCRM = 00; // Position counter reset on the index pulse
EQep1Regs.QEPCTL.bit.IEI = 10; // Position counter reset on rising edge of the index pulse
EQep1Regs.QEPCTL.bit.UTE = 1; // Enable unit timer
EQep1Regs.QEPCTL.bit.WDE = 0; // Disable the eQEP1 watchdog timer
// Position counter, capture timer, capture period values is latched
// into QPOSLAT, QCTMRLAT and QCPRDLAT register on unit time out
EQep1Regs.QEPCTL.bit.IEL = 1; // Latch on rising edge of indux [ulse
EQep1Regs.QEPCTL.bit.QPEN = 1; // Enable eQEP position counter
// Setup eQEP1 Position-compare control
EQep1Regs.QPOSCTL.bit.PCE = 0; // Disable position compare unit
// Setup eQEP1 Capture Control
EQep1Regs.QCAPCTL.bit.UPPS = 0; // Unit position event prescaler(UPEVENT = QCLK/1)
EQep1Regs.QCAPCTL.bit.CCPS = 4; // eQEP1 capture timer clock prescaler(CAPCLK = SYSCLKOUT(=150MHz)/16)
EQep1Regs.QCAPCTL.bit.CEN = 1; // Enable eQEP1 capture unit
// Setup eQEP1 Interrupt Enable
EQep1Regs.QEINT.bit.UTO = 1; // Unit time out interrupt enable
// Setup GPIO and interrupt service routine for eQEP1
EALLOW;
GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up on GPIO20 (EQEP1A)
GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up on GPIO21 (EQEP1B)
GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up on GPIO22 (EQEP1Z)
GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Sync to SYSCLKOUT GPIO20 (EQEP1A)
GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Sync to SYSCLKOUT GPIO21 (EQEP1B)
GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Sync to SYSCLKOUT GPIO22 (EQEP1Z)
GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // Assuming GPIO20 is EQEP1A
GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // Assuming GPIO21 is EQEP1B
GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // Assuming GPIO22 is EQEP1Z
PieVectTable.EQEP1_INT = &eqep1_isr; // for eQEP1 interrupt
EDIS;
// Enable CPU INT5 for eQEP1
IER |= M_INT5;
// Enable eQEP1 INT in the PIE: Group 5 interrupt 1
PieCtrlRegs.PIEIER5.bit.INTx1 = 1;
}