Hi,
I'm measuring 7.2 micro-seconds between the center (of the center aligned PWM pulses) to entering the mainISR(). This is measured by looking at the PWM pulses and setting a GPIO output at the very beginning of the mainISR().
This seems to indicate that either the ADC is not being triggered in the middle of the low side pulse, or the ADC is taking 7.2 usec to convert the seven channels.
This is a TMS320F28054M running at 60MHz with a project based on proj_Lab10b. I would expect the ADC to take less than 2 usec to convert the 7 channels (3 currents, 3 voltages, bus). I've looked closely at the ADC setup and it looks configured correctly to run at the CPU clock rate and with the minimum sample time.
Do you agree that 7.2 usec between the center of the PWMs to getting in the mainISR() seems to long?
Is there a way to actually see when the PWM is triggering the first ADC conversion?
Thanks.