I'm having a little trouble understanding the outputs of the PI controllers for Id and Iq in Lab 11, and I think there might be a fault. Here's my problem.
The saturation limits for the PI controllers for Vd and Vq (the outputs of the PI controllers) are approximately –0.5 to 0.5. These are constant values, determined at compile-time. It is explained that the -0.5 to 0.5 range allows a smoother transition from Valpha and Vbeta into the PWM duty cycles, and that all makes sense. Later, this is fed into the space vector modulator, but not before the system does DC bus compensation. The software divides by the DC bus to adjust the maximum value of the Vd and Vq variables.
However, look at what happens when we use a test scenario. Suppose Vd saturates at 0.5 (the maximum value). This will clamp Vq to zero. Also, suppose that the instantaneous flux angle is zero, and that the DC bus is 0.25pu. First, the inverse Park will directly pass Vd to Va and Vq to Vbeta, because theta is zero. Next, the bus compensation will set Valpha = 0.5/0.25 = 2 (Vbeta stays zero). Finally, Valpha =2 and Vbeta = 0 are fed into the space vector module. The outputs of the SVPWM module will be Va = 1.5, Vb = –1.5, and Vc = –1.5. Now, these values are shifted up by 0.5 by the actual PWM generator, which will result in final numbers of 2, –1, and –1. These correspond to actual duty cycles of 200%, –100%, and –100%. Obviously that can't happen, so the actual PWM generator will clamp these values. However, this will result in a terrible-looking waveform.
My thought is this: Shouldn't the DC bus compensation be an integral part of the Vd/Vq limits, instead of later down the road? After all, the actual limits for Vd and Vq are dependent on the present bus voltage, not on a pre-conceived limit. In other words, I think if we integrated the DC bus compensation to the PI saturation limits for Vd, that would prevent this problem.
Thanks,
Matt
