Question:

I would like to write back to back XD[15:0] in a single XCLKOUT cycle (buffered mode).  It looks to me like this is not possible because XWRLEAD must be at least 1 cycle, and the (confusing part) XWRACTIVE, if set, means zero wait states - not zero periods.  Do I understand correctly?  Can you suggest a way to write 16 bits on back to back XCLKOUT cycles?

Answer:

"XWRLEAD must be at least 1 cycle"

Yes, XWRLEAD must be 1 XTIMCLK cycle.

"XWRACTIVE, if set, means zero wait states - not zero periods"

Correct - the timing registers add wait states.  There is always an implied active XTIMCLK cycle so 0 means 1 XTIMCLK cycle.

"Do I understand correctly?  Can you suggest a way to write 16 bits on back to back XCLKOUT cycles?"

XWRTRAIL is also often 1 cycle.  This is to make sure the write strobes are not in transition if there is a following (back-to-back) read. 

From this the minimum would be 3 XTIMCLK cycles. Depending on the configuration XCLKOUT is equal or 1/2 of XTIMCLK.  

An access always occurs at the start of an XCLKOUT cycle, so if it is 1/2 of XTIMCLK a configuration of 3 XTIMCLK would result in a dead cycle for XCLKOUT alignment.

Can the external device on their board work with these timings - that is another question to consider.