Original Question

There's one doubting question from the PWM UG on ETPS register.

In the latest PWM UG (SPRUGE9E) P70 we can find below statement:

Writing to the INTPRD bits will automatically clear the counter INTCNT = 0 and the counter output will be reset (so no interrupts are generated).

And then in the ETPS register field descriptions in P137:

Writing a INTPRD value that is the same as the current counter value will trigger an interrupt if it is enabled and the status flag is clear.

Writing a INTPRD value that is less than the current counter value will result in an undefined state.
If a counter event occurs at the same instant as a new zero or non-zero INTPRD value is written, the counter is incremented.

It seems there're conflict betweem these two: one is going to clear INTCNT to 0 and has no interrupt if you write to INTPRD, while the other says "it depends'.

So, which one is true?

Answer:

Both instances of the user guide are somewhat. The behavior is as follows:

  • Writing an INTPRD value that is GREATER or equal to the current counter value will reset the INTCNT = 0.
  • Writing an INTPRD value that is equal to the current counter value will trigger an interrupt if it is enabled and the status flag is cleared (and INTCNT will also be cleared to 0)
  • Writing an INTPRD value that is LESS than the current counter value will result in undefined behavior (i.e. INTCNT stops counting because INTPRD is below INTCNT, and interrupt will never fire).

The initial statement on Pg 70 needs to be clarified to reflect the above.