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The F2806x maximum SYSCLKOUT frequency has changed from 80 MHz to 90 MHz.
In the device support code what should I change to reach this frequency?
The configuration you will want to use is:
#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT#define DSP28_PLLCR 18
The increase from 16 to 18 will not require an additional bit to be added to the PLLCR[DIV]. This value was previously shown as reserved as we did not intend to support a SYSCLK higher than 80 MHz. This will be shown when the TRM is updated.
The device support package within controlSUITE will be updated to reflect this change.
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