CCS/TMS570LC4357: SL_SelfTest_SRAM() is not working when running the Application!

Hello Rabie,

I have forwarded your question to our SW team. You will get response next week.

Hi Rabie Hammoud,

I noticed that you have multiple tests, is there a specific test that failed or you see the same across all SL_SelfTest_SRAM tests.

Hi Prathap,

i got the same results across all SRAM self tests. But i wonder, why these self tests are running well, when i use the Debugger, but i cannot reach the main function when i run the program without Debugger. 

Thank You

Hi Rabie

Other than SRAM PBIST test I do not see any other functions having any issue. PBIST is an issue bacuse you will wipeout all RAM contents including STACK, so this function needs special attention.. 

But I do not see any  reason for your list of API's above will have different behavior with Debugger on and Off. 

Just for Check, can you make sure the Stacks are working as it suppose to,i.e., you are not corrupting the Stacks.. 

I will try to recreate your test here and keep you posted.

Hi Prathap,

this is the code i am using to activate the Self Diagnostics. It pass untill SRAM self test. When stepping this code using the Debugger, it run well and i can reach the main().

-->

void _c_int00(void)
{

/* USER CODE BEGIN (5) */
/* USER CODE END */

/* Initialize Core Registers to avoid CCM Error */
_coreInitRegisters_();

/* Initialize Stack Pointers */
_coreInitStackPointer_();

/* Reset handler: the following instructions read from the system exception status register
* to identify the cause of the CPU reset.
*/
switch(getResetSource())
{
case POWERON_RESET:
case DEBUG_RESET:
case EXT_RESET:

/* USER CODE BEGIN (6) */
case NO_RESET:
/* USER CODE END */

/* Initialize L2RAM to avoid ECC errors right after power on */
_memInit_();

/* USER CODE BEGIN (7) */

/* USER CODE END */

/* USER CODE BEGIN (8) */
/* USER CODE END */

/* USER CODE BEGIN (9) */
/* USER CODE END */

/* Enable CPU Event Export */
/* This allows the CPU to signal any single-bit or double-bit errors detected
* by its ECC logic for accesses to program flash or data RAM.
*/
_coreEnableEventBusExport_();

/* USER CODE BEGIN (10) */

SL_Set_nERROR();
SL_Clear_nERROR();
while(SL_ESM_nERROR_Active() == TRUE);
{
/*Wait until ERROR Pin is cleared*/
}

/* USER CODE END */

/* Check if there were ESM group3 errors during power-up.
* These could occur during eFuse auto-load or during reads from flash OTP
* during power-up. Device operation is not reliable and not recommended
* in this case. */
if ((esmREG->SR1[2]) != 0U)
{
esmGroup3Notification(esmREG,esmREG->SR1[2]);
}

/* Initialize System - Clock, Flash settings with Efuse self check */
systemInit();

/* USER CODE BEGIN (11) */
#if (PBIST_ROM_ENABLE == 1U) || (PBIST_L2RAM_ENABLE == 1U) || (PBIST_PERIPHRAM_ENABLE == 1U)
/*This function is workaround for Errata PBIST#4. This function is designed to initialize the ROMs using the PBIST controller.*/
/*The CPU will configure the PBIST controller to test the PBIST ROM and STC ROM*/
errata_PBIST_4();
#endif

/*ROM Self Test*/
#if PBIST_ROM_ENABLE == 1U
{
boolean retVal;

/*Start PBIST on STC ROM and PBIST ROM */
retVal = SL_SelfTest_PBIST( PBIST_EXECUTE,
PBIST_RAMGROUP_01_PBIST_ROM |
PBIST_RAMGROUP_02_STC1_1_ROM_R5 |
PBIST_RAMGROUP_03_STC1_2_ROM_R5 |
PBIST_RAMGROUP_04_STC2_ROM_NHET,
PBISTALGO_TRIPLE_READ_FAST_READ |
PBISTALGO_TRIPLE_READ_SLOW_READ);
/*Fail to start*/
if(retVal == FALSE)
{

While(1);

}

SL_PBIST_FailInfo pbistStatus;

/* Wait for PBIST on ROM to complete */
while(SL_SelfTest_Status_PBIST(&pbistStatus) == FALSE);
SL_SelfTest_PBIST_StopExec();

if(pbistStatus.stResult != ST_PASS)
{
/* PBIST fail */
while(1);
}

/* Clear VIM pending interrupt request (Channel 85 - PBIST Done) */
vimREG->INTREQ2 = 0x00200000;
}
#endif

/*CPU RAM Self Test*/
#if PBIST_L2RAM_ENABLE == 1U
{
/* Run PBIST on L2RAM */
SL_SelfTest_PBIST( PBIST_EXECUTE,
PBIST_RAMGROUP_29_L2RAMW |
PBIST_RAMGROUP_30_L2RAMW,
PBISTALGO_MARCH13N_1PORT);

while((systemREG1->MSTCGSTAT & 0x1u) == 0x0u);

if ((pbistREG->FSRF0 == 0u) && (pbistREG->FSRF1 == 0u))
{
/* PBIST pass */
}
else
{
/* PBIST fail */
while(1);
}

/* Disable PBIST clocks and disable memory self-test mode */
SL_SelfTest_PBIST_StopExec();
_memInit_();

/* Clear VIM pending interrupt request (Channel 85 - PBIST Done) */
vimREG->INTREQ2 = 0x00200000;
}
#endif

#if L2RAMECCCHECK_ENABLE == 1
{
boolean retVal;
SL_SelfTest_Result result;

retVal=SL_SelfTest_SRAM(SRAM_RADECODE_DIAGNOSTICS, TRUE, &result);
if(retVal == FALSE){while(1);} /*Fail to start*/
if(result == ST_FAIL)
{
/*ST Failed*/
while(1);
}

retVal=SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_1BIT, TRUE, &result);
if(retVal == FALSE){while(1);}
if(result == ST_FAIL)
{
/*ST Failed*/
while(1);
}

retVal=SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_2BIT, TRUE, &result);
if(retVal==FALSE){while(1);}
if(result == ST_FAIL)
{
/*ST Failed*/
while(1);
}
}
#endif

Thank you for helping

Hi Rabie

Not sure if you have made any progress on this? I do not see a failure.

Let me know if you still need assistance with the issue. 

Hi Prathap,

i didn't achieve any progress in that issue. Did you try to run the code, i sent it to you?

I am wondering why this piece of code is running well, when i use the Debugger, but it fails to reach the main() without the Debugger.

I hope we could solve this Problem

Hi Rabie,

I tried same API's in different device, but not on the TMS570LC4357. Hope I could get some board tomorrow and send you a sample project.

Couple of things I would like to to try
1) When you connect after the failing scenario, where does the PC control, is it in some abort handler or some where stuck.
2) If you notice any ESM errors ( look at the ESM register), let us know what all errors are set.
3) Also try the suggestions I gave on a different device, if the control is going to prefetch abort.... e2e.ti.com/.../2391369

Hi Prathap,

the function SL_SelfTest_SRAM(SRAM_RADECODE_DIAGNOSTICS, TRUE, &result) is working well. The other 2 functions :

- SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_1BIT, TRUE, &result) and SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_2BIT, TRUE, &result) are still having the same issue.

After a fail start the following is represented in the ESM: 

As you can see there is no errors in the ESM.

I am using the following settings in my CSS project:

 

I did activate the Auto ECC Generation, but without any results. 

Did you have any progress? 

Hi Rabie 

I did a simple example for the selftest SRAM. It worked fine. 

please find it attached. /cfs-file/__key/communityserver-discussions-components-files/312/2350.SL_5F00_LC43x_5F00_SampleCode.zip