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CCS/TMS570LS3137: How to Dynamic change PLL output frequency

Jeff Chen71
Expert 1345 points
Part Number: TMS570LS3137

Tool/software: Code Composer Studio

Hi ,

    My customer using spna193 uart bootloader for tms570ls313x, when he jump to app the uart is not working.

I found the pll setting between boot and app was different if pll register set to same value it work well.

But they want to know why pll fail initialize in app .And  how to dynamic change pll output frequency.

Thanks 

B.R.

Jeff Chen

  • 0
    TI__Guru**** 186196 points
    Hello Jeff,

    Once the valid bit (CLKSRnV bit in the Clock Source Valid Status Register (CSVSTAT) of the System and Peripheral Control Registers) is set, software may change values to the PLL. If the change of values results in a small percentage change to the VCO frequency (ΔfOutputCLK < 0.1 × fOutputCLK), then these changes can be done on-the-fly. In this mode, the values are updated into the PLL synchronously, and the PLL re-locks to the new value without gating the clocks or the slip bits. If the operating point change is too large, then the slip bits will be set.

    Conversely, if the changes to the VCO frequency are large, then the PLL should be disabled prior to changing the values. Typically, any change to the REFCLKDIV field or large changes to the PLLMUL field in the PLL Control Register 1 (PLLCTL1) of the System and Peripheral Control Registers requires a complete disable-and-relock strategy.