Hello Karl,
I found the following statement in your reply:
"Ensure that you see the fail noted in both the CPU (via prefetch or data abort) and on the ESM."
Can you please elaborate somewhat more on how to see fail results individually for two CPUs?
I thought they are in Lockstep mode and hence you can't access individual register bits.
Thank you.
Regards
Pashan
Hello Pashan,
I think you misunderstand my statement - I am saying both in terms of (CPU) and (ESM). You are correct that you cannot access the master and checker CPU separately in this architecture.
Regards,
Karl