Hello TI-Engineers/Forum,
I am developing a Board for usage in mass transportation systems where certification of the whole system is necessary. For the fulfillment of various (European) Standards, I need to conduct a HAZOP (hazard and operability study) Analysis. My preferred MCU is the TMS570LS3137.
As a result of the HAZOP there are appeared a few questions regarding the internal memory protection of data:
+ How can the TCRAM detect a complete failed write (logical memory cell is not updated entirely, so during the next read access outdated data will be read.)
+ How can the TCRAM detect a complete failed read (RAM cells are disconnected from the Bus.)
+ In the Safety Manual for the TMS570LS20216S, V1.0.4 there is mentioned that **NDA Material - removed from the public post by TI**
What are the defense mechanisms for these threats?
To my own understanding:
+ In the Hercules Safety Manual SPNU511, Fig. 8 there is mentioned that the 2 TCM Busses are EVEN Address and ODD Address separated. Is the transfer to/from memory executed in parallel?
+ Are the two Busses B0TCM and B1TCM connected to each of the cores (Master CPU and Checker CPU) or is each Bus exclusive for one CPU core? Exists there a more detailed figure of this matter?
+ When a write is executed, whose CPU (Master or Checker?) data will be written?
+ TRM Question: In the document (SPNU499) in p.302, Fig. 6-2 there is mentioned that the logical address space starts at 0MB and end at 0MB+256kB. The implemented ECC space starts at 4MB and ends at 4MB+256kB. Why is the ECC space as big as the data space? Shouldn’t the ECC space just be one eight of the data space?
Regards and thank you for the answers in advance
Lorenz
Hello Lorenz,
KG> Failure of SRAM which can cause both cases noted can be detected to >99% DC with the PBIST testing recommended for use at startup. In addition, the TCM ECC/parity should be able to detect most failed read/write operations.
KG> All TMS570LS derivatives to date use the same TCM ECC scheme.
KG> There are three TCM masters (instruction, data, and slave (DMA) port) and three slaves (ATCM - flash, B0TCM - even 64b addressed SRAM, B1TCM - odd 64b addressed SRAM). It is possible to have three TCM accesses completing in parallel at any time, two of which are SRAM accesses. The two SRAM TCMs feature interleaved addressing on 64b boundary to improve throughput.
KG> No. The logical CPU has 3 TCM interfaces, as does the checker. Please refer to the ARM Cortex R4 TRM.
KG> All writes are from the logical CPU. The checker CPU's outputs go only to the comparator logic.
KG> In the current generation of product, the ECC data is not packed. This allows the user an easy way to find the ECC data, by simply adding the address in question + 4MB. The ECC data is then mirrored across all bytes of the 64b data word in the ECC space, as noted on the page you reference.
Best Regards,
Karl