My customer would like to clarify about the jitter value of the ECLK output (@20MHz) in TMS470MF06607.
Is there any characterized data of the jitter value on ECLK of TMS470MF06607 ?
Or, is there any calculation methodology to figure out the jitter value for ECLK, like a TMS470 App. note; Impact of ZPLL Jitter on CAN Communicatiohttp://www.ti.com/lit/an/spna070a/spna070a.pdf ?
Thanks and Best Regards,
thank you for your post. One of our experts will get back to you soon.
While waiting for our experts, let me clarify some points.
1, The best way to get a low jitter ECLK is to output the oscillator clock through ECLK. For example, if you want a 20MHz ECLK, then use a 20MHz crystal, and put the oscillator as the ECLK source. In this case, the ECLK jitter is dependant on the crystal that you use. Based on my experience 3 years ago on another device (same oscillator and PLL module), the ECLK jitter std value is around 10-20ps.
2. If you choose PLL as the HCLK and VCLK source, and then divide the VCLK down as the ECLK output, then the ECLK jitter is dependant on the crystal and the PLL setting. The PLL jitter can be minimized by:
NR is the input clock divider, which controls the frequency of the adjust pulse. A lower NR value means the error in PLL frequency is compensated faster, resulting in less jitter. The adjust pulse will go through a low pass filter (LF) before it applies to the VCO. The cut-off frequency of this low pass filter is controlled by the BWADJ field inPLLCTL2 register. A lower BWADJ value results in less jitter. During normal operation, any BWADJ less than 7 will be treated as 7. A Larger NF also generates less jitter.
Thank you for your explanation.
I just would like to clarify of the phrases; "A lower NR value" means small divisor ?
"A larger NF" means big divisor ?
Regarding ECLK jitter spec or observation methodology, I'm still expecting for any feedback from your expert.
Let me give an example:
Suppose the Crystal freq is 20MHz and you want an HCLK 80MHz, to minimize the jitter:1. The INTCLK should < 6.53MHz. So, choose NR=4. INTCLK=20/4=5MHz.
2. We want NF as big as possible: the Output of PLL (before divisor) is 500MHz maxium according to the user guide, So, NF=480MHz/5MHz=96
3. According to the datasheet the RCLK should be <145MHz, so, we have to set it to 80MHz. OD=6, R=1.
4. Eventually, we get: 20/4*96/6/1=80MHz.
5. Of cause, to minimize the jitter, you have to disable the FM mode and set BWADJ=7.
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Very sorry for my long delay of response. This is solved.
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