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TMS570 TCRAMW Redundant Address Decode Logic Test
I have been trying to use the TCRAM wrapper test mechanism to verify behavior of the redundant address decode and compare logic. I have run into some confusing results.
To start off, I make sure to clear the appropriate registers like RAMUERRADDR, RAMERRSTATUS, set a test address in RAMADDRDECVECT, and enable and set the test mode to an inequality test in RAMTEST. I then trigger the test by writing to the appropriate pin in RAMTEST. So far so good...
I run the test on B0TCM, and then on B1TCM (while debugging). Here are the issues I see:
1) RAMMERRSTATUS bit that gets raised is ADDR DEC FAIL, (bit 2), not ADDR COMP LOGIC FAIL (bit 4), as the TRM says.
2) The first test (B0TCM), RAMERRSTATUS is read and cleared properly, but the appropriate ESMSR2 channel also gets raised. However, even though this channel is raised, the ERROR pin is not driven low as expected.
3) The second test (B1TCM), RAMERRSTATUS is viewed to have been raised in my debugger, but when my code tries to read it, it comes out as cleared. The appropriate ESMSR2 channel is also raised, except this time the ERROR pin IS driven low.
When I repeat the test, switching the order so I test B1TCM first and then B0TCM, I see the opposite (so B0TCM and B1TCM are no different, its whoever is tested first acts likt step (2) and whoever is tested second acts like step (3).
My direct questions are:
(A) Is it correct to expect a RAMERRSTATUS ADDR DEC FAIL instead of a ADDR COMP LOGIC FAIL?
(B) Why does the Group 2 ESM signal of the first test not trigger the ERROR pin while the second test does? I thought all Group 2 ESM signals were fixed to lower the ERROR pin.
(C) Why can my first test read RAMERRSTATUS correctly while my second test cannot? (These are different registers in memory too, so I dont know why the order matters).
The only similarity I can think of is I use the same test address in RAMADDRDECVECT.
Update: Question B had to do with a error in another part of the code ... make sure to write 0x0 back to your ESMEKR register after using to force the ERROR pin high or low!
I'm forwarding your questions to the designers of the TCM SRAM wrapper for further review.
Can you please confirm on how you write to the test trigger bit of the RAMTEST register?
Do you write TRIGGER, TEST MODE, TEST ENABLE at the same time for the first BxTCM that you tested?
It is recommended to write TRIGGER alone after TESTMODE / TESTENABLE are updated.
If my reply answers your question please click on the green button "Verify Answer".
sorry it takes sometimes to response to you. We were retesting our silicon with different scenarios and recreating your scenarios to make sure we have the right answer for you.
i will attempt to answer RAM Address Redundant Comparator test and ESM Error Pin toggle separately as these are two separate scenarios.
RAM Address Redundant Comparator Test:
For equality test,
- If the comparator matches (no true silicon fail), there is no status bit set for ADDR COMP LOGIC FAIL or ADDR DEC FAIL.
- If there is true silicon malfunction, ADDR COMP LOGIC FAIL & ADDR DEC FAIL will be set, no UERRADDRESS is captured.
For inequality test, the compare vector will not match since non-inverted and inverted values of the same test vector are fed to the comparator.
- If there is no silicon malfunction on any of the comparator bits, then only ADDR DEC FAIL will be set. This is chosen so that we can ensure the functional ADDR DEC FAIL status bit data path can be tested.
- If there is a silicon malfunction on any of the comparator bits, then, ADDR COMP LOGIC FAIL & ADDR COMP LOGIC FAIL will be set, no UERRADDRESS is captured.
So in your test, you only observe ADDR DEC FAIL status bit in the inequality case indicates that the test passes (no malfunction).
ESM Error Pin Toggle Test:
To properly explain your observation, we need to explain in high level how the counter, key, and error pin behaves.
How counters work:
- System reset causes a counter pre-load.
- Counter starts decrementing whenever there is a fail occurs on the right group until counter=0x0.
- Once (counter =0x0 & key = 0x5) Or (key = 0xA) Or (there is a new fail), it will reload back to pre-load value else counter will remain at current values.
The new fail occurs which causes a reload will cause the counter to start decrementing after reload completes.
How the key works:
- System reset causes key = 0x0
- Key can be update by User; be aware of additional note below:
- Once counter = 0x0 and key is 0x5, then, key will auto reset to 0x0.
How nERROR pin behaves based on counters and key:
- Power on reset will assert nERROR pin to 1.
- nERROR pin remains in previous value on system reset. However, after system reset is released, values of key, counter may impact nERROR pin.
- Out of system reset,
On your test, you probably have the test key still set at 0x5 because this is how you will pull up the nERROR pin after forcing error by writing 0xA to key register.
On your first BxTCM address redundant comparator test, the error pin asserted low and pulls back high with 0x3FFF* VCLK cycles. This is very fast to observe the LED light to light up. If you look at the scope on nERROR pin, you will see that it asserts low and pulls up high.
However, the KEY will be auto reset back to 0x0 which is the normal mode after the first BxTCM address redundant test (from the above definition).
So on the second BxTCM test, since the key is reset to 0x0, once the nERROR pin is asserted low, it will remained low until you cleared it again by writing 0x5 to key register.
Error detected on group 2 and group 3 will automatically causing a reaction on nERROR pin.
I hope this helps you,
Please let us know if you need further clarification on this.
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