Usually in the device datasheet, there is a Functional Block Diagram for the device which shows DAP-JTAG Connection with all the other Blocks over different BUS/SWITCH mechanism.
In the TMS570LS3137 Device Datasheet, Section 1.4 has Functional Block Diagram which is missing DAP-JTAG Pins and its relation with other Blocks like RAM/CPU and so on.
Please help me with the updated Functional Block Diagram like TMS470R1x ARM7TDMI devices.
As devices become increasingly more complex and with greater content, it has become more and more difficult to provide 100% of the detail within the single block diagram. As a remedy, we have added sections to the datasheets to highlight some functionality such as the debug architecture. In this case, the debug connection details are shown in section 4.21.1, figure 4-19 (SPNS162 - September 2011). The level of detail offered in this diagram is greater than what was provided in previous dataheets for the ARM7TDMI.
Please have a look at this section and let us know if it provides the information you need.
Thanks and Regards,
If this response answers your question, please indicate it by verifying the suggested answer when provided.
In spns162.pdf :
From DAP there is outgoing connection to "to SCR1 via A2A" and incoming connection from "from PCR1/Bridge" within the picture you mentioned.
I am assuming that is not for CCM-R4 core because that is being shown as a different connection.
So, what does that "to SCR1 via A2A" and "from PCR1/Bridge" mean?
Where does that go?
Any better description will help me to understand.
The connection to SCR1 via A2A is a connection between the DAP and the main SCR (Switched Component Resource) through the A2A bridge. Generally speaking, the A2A is an internal bus protocol translator between the DAP and the SCR. The SCR is a switch that manages accesses on the main system bus. This connection allows access through the DAP to the TCMs and CPU registers without halting the CPU. SCR1 is represented in the main block diagram by the block labeled "Main Cross bar: Arbitration and Prioritization Control."
The connection from PCR1/Bridge is allows accesses between the debug ROM and the Cortex R4.
Typically speaking, these components are not something that you will need to be worried about in your system development unless there is some issue with tool compatibilty or tool development.
In the picture I see "DEBUG APB" connection going to Debug ROM and Cortex-R4.
But in the mail, you are saying " PCR1/Bridge is allows accesses between the debug ROM and the Cortex R4.".
Which one is Correct? Picture in the Datasheet or your mail reply?
May be you can cetgorize the function individually for each of the following names as shown in the Picture of Datasheet:
"Debug APB" "to SCR1 via A2A" and "fromPCR1/Bridge".
This will help me understand better.
I understand the confusion. The Debug APB connection is for debugger access to the debug ROM. By default, we cannot access the memory mapped debug components (including cpu registers, etm, tpiu, and others). As a way around this, we mapped them to our PCR (base address 0xFFA0_xxxx). Any access coming from PCR1/bridge arbitrates between the debug apb access and gives access to all IPs. So the answer to your question is that both the diagram and my description are correct.
The description of the SCR1 connection remains the same. The intent of this connection is to provide non-invasive access to the device memories by the debugger.
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