Hello,I am trying to make sense of the ADC self test section in the TMS570LS31x/21x TRM (SPNU499 Sept 2011). I hope you can clarify!
Firstly I think table 18-3 is wrong. S5 should surely be 0 when in self test mode.
Table 18-4 is also extremely confusing. In the last row, how can a conversion result be unknown? I think it probably means "none of the above".
The term "ADC Input Channel" is also confusing in section 188.8.131.52 because I am fairly sure the TRM is referring to the input to the ADC Core, not to the input to the ADC multiplexer. Otherwise I can't see how a short at the multiplexed input would cause a conversion of a reference voltage to be wrong.
Finally, the implication is that for the self test to work as described in section 184.108.40.206 you have to know in advance what the input voltage is.
The self-test mode is specifically designed to identify issues on the path from the analog input terminal to the ADC core. The logical switch S5 shown in figure 18-12 and referenced in table 18-3 is closed during a conversion in self-test mode. This effectively allows the external analog input to be connected to the ADC core input at the same time as the chosen reference voltage.
The term "Unknown" in table 18-4 needs to be replaced with "don't care". This will be done in the update to the TRM.
This scheme for identifying issues with the input path does have some limitations. For example, it does not work well with external input levels very close to ADREFHI or ADREFLO. The scheme works well for external input voltages in the range between ADREFLO and ADREFHI.
Hi Sunil,Thanks for the response but I still don't understand. If S5 is closed then in test mode you have the multiplexed input pin connected directly to the ADC core in parallel with ADREFHI or ADREFLO connected through 5K and 7K resistors.
If the output impedance of the buffer driving the ADC pin is low then ADREFHI and ADREFLO will have little effect on the voltage seen by the ADC core.
Am I missing something here?
In that case, the conversion results Vu will be just slightly higher than Vn and Vd will be just slightly lower than Vn (referring to table 18-4). The application can use this information to determine that the input path is okay.
OK I think I understand.
Reading the datasheet it appears that the maximum on resistance of both mux and sample switch is 250R making a maximum on resistance of 500R. So even if there is a short at the pin you would expect a small difference when you close S2/S3 or S1/S4. But I see your point that even with a low output impedance on the buffer feeding the ADC input we should be able to tell the difference between a working and a failed input.
I will give it a try with our hardware and see what the data looks like.
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