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Pashan,

The VIM module supports edge triggered interrupt, but this is transparent to the end user.

A majority of our peripheral modules are level interrupt, some are edge interrupt.
Because of this mix, the VIM can comprehend both.

Can you explain what are you trying to achieve?

For information, the ARM document you are using is useless in our case. We developed our own interrupt module (VIM).
Please refer to our TRM to see and understand how interrupt are handle within the VIM.

Thanks and Regards,

Jean-Marc

Hello Jean-Marc,

I am assuming following steps are needed in order when level-triggered INTREQ Pin is active:

1> ISR Code starts execution because of LDR pc, [pc, #-0x1B0]  ----  Effectively reading FIQVECREG -- I am assuming FIQINDEX is not cleared

2> ISR Processing

3> Peripheral Interrupt Flag Clear

4> Read FIQINDEX to clear VIM ISR Flag  -- Because Level Triggered so new INTREQ will remain active

I am asuming Step 1 above doesn't clear FIQINDEX Register

****************************************************************************************************************************************

For Edge-Triggered case of INTREQ Pin:

1> ISR Code starts execution because of LDR pc, [pc, #-0x1B0]  ----  Effectively reading FIQVECREG -- I am assuming FIQINDEX is not cleared

2> Read FIQINDEX to clear VIM ISR Flag  -- Because next edge of INTREQ might occur which will be missed

3> ISR Processing

4> Peripheral Interrupt Flag Clear

Hence, my question is which order above should I follow during INTREQ processing?

Any more information will be helpful for my understanding.

Thank you.

Regards

Pashan

Pashan,

From a software/user point of view, level and edge trigger interrupts are used the same way.

1] The IRQVECREG or FIQVECREG as to be accessed to get the address of the ISR routine. This will clear the hold logic within the vim module.
    The hold logic in the VIM is used is in fact an edge detector that will apply for both pulse and level interrupt request.
    The read from IRQVECREG or FIQVECREG is done during the execution of LDR pc, [pc, #-0x1B0] for the vector mode, or directly by the CPU when the VIC mode is used (To be enabled in the CPU via CP15)   

2] In the corresponding ISR, the interrupt flag has to be cleared. (At peripheral module level) This will clear the request to the VIM module.

The main difference between level and pulse will be during step 2,.
Within the ISR routine, if the corresponding flag is not cleared, the request will stay active to the VIM for a level based interrupt peripheral module.
In this case, when the CPU exits the exception mode, it will re-enter in exception again until the source interrupt is cleared.
This is not the case for a pulse based peripheral module.
On the EMAC (Ethernet) module, interrupt are pulse. Once the EMAC control module has issued an interrupt pulse to the VIM, it will not generate further pulses of the same type until the original pulse has been acknowledged.

Please let me know if this clarify your question.

Thanks and Regards,

Jean-Marc

Hello Jean-Marc,

1> FIQINDEX or IRQINDEX will also be cleared automatically due to LDR pc, [pc, #-0x1B0] instruction?

2> Other than Ethernet (EMAC), which peripherals are PULSED Mode of INTREQ to VIM?

Thank you.

Regards

Pashan

Pashan,

1) Yes,

2) EMAC, USB, EMIF, ePWM, eCAP, eQEP as top of my head. I've asked our design IP team to come up with a full list.

Again, if the procedure to reply to interrupt is done correctly, than this is transparent.

Regards,

Jean-Marc

Hello Jean-Marc,

Did you get the full list of Peripherals having Pulsed Mode INTREQ from your design team as mentioned by you in the last mail trail above?

Thank you.

Regards

Pashan