The behavior of the TMS570 and its terminations.

Hi,

I have questions related to the Hercules mcu (TMS570LS2125).
Could you answer the following questions?

1. When I don't connect FLTP1, FLTP2 and TEST termination, what do the terminations work?
   I wonder if no connect (NC) occurs the bad influences.

2. When the VCC (1.2V) terminations and the nPORRST termination are shorted, what will happen?
   Does the reset circuits will never be activated by the nPORRST termination?

3. When the VCCP termination and the VSS (GND) terminations are shorted, what will happen?
   And in the above case, what does the cpu behave?
   I wonder if the flash and the mcu work safety.

thanks

Nomoto

  • Yusuke Nomoto

    Hi,

    I have questions related to the Hercules mcu (TMS570LS2125).
    Could you answer the following questions?

    1. When I don't connect FLTP1, FLTP2 and TEST termination, what do the terminations work?
       I wonder if no connect (NC) occurs the bad influences.

    FLTP1 and FLTP2 should be NC. TEST should connect to GND. TEST has an internal pull down, therefore, if it is not connect to GND, the MCU still work but may fail in immunity/ESD test (huge environmental noise).

    2. When the VCC (1.2V) terminations and the nPORRST termination are shorted, what will happen?
       Does the reset circuits will never be activated by the nPORRST termination?

    Based on datasheet, it is the gray area, the MCU may treat it as high or low.

    3. When the VCCP termination and the VSS (GND) terminations are shorted, what will happen?
       And in the above case, what does the cpu behave?
       I wonder if the flash and the mcu work safety.

    thanks

    Nomoto

  • In reply to Haixiao Weng:

    Haixiao,

     

    Thank you for the answer of the question 1 and question 2.

    And could you answer the question 3?

     

    Then, I have a additional question.

    4. When the nRST termination and the nERROR termination are shorted, what will happen?

      And in this case, what does the cpu behave?

     

    thanks

     

    Nomoto

  • In reply to Yusuke Nomoto:

    Yusuke Nomoto

    Haixiao,

     

    Thank you for the answer of the question 1 and question 2.

    And could you answer the question 3?

     HW: if VPP is short to ground, the flash module will never provide a ready signal and the CPU will be held on reset (based on design spec). So the pins will remain in the default state.

    Then, I have a additional question.

    4. When the nRST termination and the nERROR termination are shorted, what will happen?

      And in this case, what does the cpu behave?

     HW: If there is an external pull up on nRST, then, our device can still power up and work. See, after power up, the nERROR become a output pin after the nRST goes high. However, now, if an error ocurrs and the nERROR goes low, and then since nERROR is connected to nRST, our device will be hold on nRST for ever: the nERROR is low, nRST is low, most of the pin are in input mode.

    thanks

     

    Nomoto

  • In reply to Haixiao Weng:

    Haixiao,

    Thank you for the answer of the question 3 and question 4.
    However, I need additional knowledge for the question 1 and the question 4,
    so could you answer following 5 questions?

    1.1 Could you teach me the recommended pull-up resistance value?

    1.2 Could I connect FLTP1 and FLTP2 to TEST termination which is connected GND?
        This is written in the data sheet.

    1.3 If FLTP1 and FLTP2 must be NC, could you show me termination equivalent circuit ?

    4.1 How much the external pull-up resistance should I connect, in case "If there is an external pull up on nRST" ?

    4.2 When the nRST termination and the nERROR termination, how can I pull down the nERROR termination without pulling nRST to low?

    thanks

    nomoto

  • In reply to Yusuke Nomoto:

    Yusuke Nomoto

    Haixiao,

    Thank you for the answer of the question 3 and question 4.
    However, I need additional knowledge for the question 1 and the question 4,
    so could you answer following 5 questions?

    1.1 Could you teach me the recommended pull-up resistance value?

    HW: Sorry, which pin?

    1.2 Could I connect FLTP1 and FLTP2 to TEST termination which is connected GND?
        This is written in the data sheet.

    HW: which datasheet? I check a few datasheet, they all says it should NC (no connection).

    1.3 If FLTP1 and FLTP2 must be NC, could you show me termination equivalent circuit ?

     

    4.1 How much the external pull-up resistance should I connect, in case "If there is an external pull up on nRST" ?

    HW: 1k-5kohm

    4.2 When the nRST termination and the nERROR termination, how can I pull down the nERROR termination without pulling nRST to low?

    HW: the nError internal pull down is very weak. Just treat it as a 10k ohm resistor. the internal pull up resistor on nRST also looks like a 10k resistor. So, the final result will depend on any pull up of external resistor.

    thanks

    nomoto

  • In reply to Haixiao Weng:

    Haixiao,

    I'm sorry but I missed some information.

    1.1 Could you teach me the recommended pull-up resistance value?
    HW: Sorry, which pin?

        The pin is the TEST termination.


    1.2 Could I connect FLTP1 and FLTP2 to TEST termination which is connected GND?
        This is written in the data sheet.
    HW: which datasheet? I check a few datasheet, they all says it should NC (no connection).

        I'm checking spns164.pdf. (http://www.ti.com/lit/ds/spns164/spns164.pdf)
        In page 19, the "Description" of FLTP1 and FLTP2 is described as
        "For proper operation these terminals must connect only to a test pad or
         not be connected at all [no connect (NC)]."
        I think that "test pad" means the TEST termination.
       

    1.3 If FLTP1 and FLTP2 must be NC, could you show me termination equivalent circuit ?


    thanks

    nomoto

  • In reply to Yusuke Nomoto:

    Yusuke Nomoto

    Haixiao,

    I'm sorry but I missed some information.

    1.1 Could you teach me the recommended pull-up resistance value?
    HW: Sorry, which pin?

        The pin is the TEST termination.

    HW: TEST pin should be short to ground in the PCB. The on-die pull - down is around 10Kohm.


    1.2 Could I connect FLTP1 and FLTP2 to TEST termination which is connected GND?
        This is written in the data sheet.
    HW: which datasheet? I check a few datasheet, they all says it should NC (no connection).

        I'm checking spns164.pdf. (http://www.ti.com/lit/ds/spns164/spns164.pdf)
        In page 19, the "Description" of FLTP1 and FLTP2 is described as
        "For proper operation these terminals must connect only to a test pad or
         not be connected at all [no connect (NC)]."
        I think that "test pad" means the TEST termination.
       HW: test pad example: a 0.3mm radius round metal. It provide a test point for debug usage. You can find many these test pad in a typical ECU.

    1.3 If FLTP1 and FLTP2 must be NC, could you show me termination equivalent circuit ?


    thanks

    nomoto

  • In reply to Haixiao Weng:

    Haixiao,

    For 1.1, I'm sorry but I mistake pull-up for pull-down.
    So, may I ask one more question?
    Isn't the pull-down register needed for the TEST termination?
    If needed, could you teach me the recommended pull-down resistance value?

    For 1.2, I could understand the meaning of
    "For proper operation these terminals must connect only to a test pad or
     not be connected at all [no connect (NC)]".
    So, could you show me the termination equivalent circuit?

    thanks

    nomoto

  • In reply to Yusuke Nomoto:

    Yusuke Nomoto

    Haixiao,

    For 1.1, I'm sorry but I mistake pull-up for pull-down.
    So, may I ask one more question?
    Isn't the pull-down register needed for the TEST termination?
    If needed, could you teach me the recommended pull-down resistance value?

    HW: the pull down inside the die is hard -coded. No way to adjust. Externally, I recommend to short the pin to GND directly.

    For 1.2, I could understand the meaning of
    "For proper operation these terminals must connect only to a test pad or
     not be connected at all [no connect (NC)]".
    So, could you show me the termination equivalent circuit?

    HW: Inside the die, by default, the tri-state buffer is inactive, in other words, it is high impedance mode.

    thanks

    nomoto

  • In reply to Haixiao Weng:

    Haixiao,

    Thank you for your answers.
    For 1.2 (equivalent circuit), I could image the structure of the equivalent circuit basically.
    However, I want to understand concretely.
    So, could you explain me the equivalent circuit with some figures?


    Then, I need additional knowledges for the case that the VCC (1.2V) terminations and
    the nPORRST termination are shorted.
    Could you answer the following 2 questions?

    2.1 When the nPORRST termination is hold on to High (because shorted to VCC),
        can I reset the device by using the warm reset?

    2.2 When the VCC (1.2V) termination and the nPORRST termination have been shorted before power-up,
        is the device hold on the cold reset?

    thanks

    nomoto