I perform the following steps to perform Check for Redundant Address Decoding error within BTCM Port :
RAMECCREG.RAMTEST.word = (0x01U << 6) | 0x0AU; /* BTCM0 */ RAMECCREG.RAMTEST.word = (0x01U << 8) | (0x01U << 6) | 0x0AU; /* BTCM0 */
I get RAMECCREG.RAMERRSTATUS.word Bit 2 as SET and ESM Group 2 Channel 6 [Even Bank] as SET
Then I write Bit 2 as HIGH within RAMERRSTATUS Register and also Clear ESM Group 2 Channel 6 Bit by writing HIGH.
Do I have to clear any other register within RAM Register SET in order to keep BTCM Port responsive to real errors at the end of the above mentioned Checking of BTCM Port?
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All uncorrectable errors on accesses to tightly-coupled CPU RAM cause the faulting address to be captured in the TCRAM module status registers. This register does need to be cleared before the TCRAM module can respond to future uncorrectable RAM errors. The device TRM's "Tightly-Coupled RAM Interface Module" chapter details this mechanism.
The application note and accompanying example code for the safety initialization sequence (SPNA106) will also be updated to reflect this requirement.
I couldn't find any section related to RAMTEST Register based ADDRESS Decoder Testing sequence within spnu517.pdf TRM.
My question is at the end of the above mentioned steps for testing using RAMTEST Register, do I have to read [MUST]1> only RAMUERRADDR Register in order to unfreeze the last error capture or2> RAMUERRADDR and RAMSERRADDR Registers bothor3>only RAMSERRADDR Registeror4>neither of RAMSERRADDR and RAMUERRADDR registers [Don't CARE]?Which one case from the above is TRUE?
Attached Page from TRM [spnu517.pdf] about the confusion. I think it is telling that Option 4 of the last mail during RAMTEST Register based testing.Please confirm which Option from the last mail is TRUE for this RAMTEST based testing.Thank you.RegardsPashan
For clearing the error flags set by the redundant address decode fail caused via the RAMTEST register, you do not need to read the RAMSERRADDR or the RAMUERRADDR registers.
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