Part Number: RM57L843
I have a working nominal MibSPI loopback implementation and I am trying to use the 27.3.42 I/O-Loopback Test Control Register (IOLPBKTSTCR) to Inject the Various errors during the test.
The only error that I have been able to successfully inject is:
Bit  CTRL BITERR Controls inducing of BITERR during I/O loopback test mode. 0 Do not interfere with looped-back data. 1 Induces bit errors by inverting the value of the incoming data during loopback.
Bit  BITERR in the RX Ram Flags
Is there any supplemental documentation around mibspi loopback fault injection that I can follow? Does SPI need to be set up in a specific way for the fault injection to work?
Any information would be helpful.
I am specifically looking to implement a functionality check of:
27.3.42 I/O-Loopback Test Control Register (IOLPBKTSTCR)
19 CTRL DESYNC Controls inducing of the desync error during I/O loopback test mode.
17 CTRL TIMEOUT Controls inducing of the timeout error during I/O loopback test mode.
16 CTRL DLENERR Controls inducing of the data length error during I/O loopback test mode.
But would like more information if available on:
18 CTRL PARERR Controls inducing of the parity errors during I/O loopback test mode.
2 CTRL SCS PINERR Enable/disable the injection of an error on the SPISCS[3:0] pins. The individual SPISCS[3:0] pins can be chosen using the ERR SCS PIN field.
5-3 ERR SCS PIN Inject error on chip-select pin number x.
In reply to Dmitri Zakharevski59:
Thanks and Regards,
In reply to Chuck Davenport:
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