Part Number: TMS570LC4357
I am looking for more details on the exact behavior of the SDRAM controller of the EMIF.
In particular, I would like to understand if really all read/write accesses start with an ACT command, or if the memory controller is first checking if the row/bank is already open and then proceeds to the read/write operation skipping the ACT.
Also it's not clear to me when an open row is closed since auto precharge is not used.
Any information will be appreciated.
Thanks and Regards,
In reply to Chuck Davenport:
As a follow up question, I would like to know if a read burst can be interrupted by a write command. This case is not listed in the TRM, but it seems strange to me.
In case a read burst can be interrupted by a write, I would like to know if the DQM signals are used to start the bus turnaround.
In reply to Mathieu Patte:
Would it be possible to have an answer on this point ?
Thanks, I just wanted to make sure that this thread was till active.
Thanks for keeping me posted. I shall wait!
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