Hercules™ Safety Microcontrollers Forum - Recent Threads

Accessing DMA working registers - Current Transfer Count Register (CTCOUNT)

J Joson — Mon, 20 May 2013 21:26:39 GMT

Hello,

I am trying to acquire a 'lot' of data with 570LS1227. DMA is triggered in hw to transfer a 16 element burst every 3 us. I want to avoid any interrupts and I allocated a 1K deep buffer for the data. Instead of waiting for a periodic interrupt (HBC/BTC) I would like to poll DMA's working register to process any new data collected in the background loop. But none of the working registers are updated during/after the transfer! There is only one active DMA channel in the system during this test.

Is there any trick to update the active working registers?

Thanks,

Joe.

FreeRTOS + RM48 HDK

Jay Khandhar — Thu, 16 May 2013 05:37:25 GMT

I am trying to run FreeRTOS on the RM48HDK. I am following the help file named example_freertosblinky.c . But the LED does not seem to blink.

First I create a empty project in Code Composer Studio. I select the variant to be RM48L950, and connection as Texas Instruments XDS100v2 USB Emulator. I leave the other settings to their default fields.

Then in HALCOGEN, I select the device as RM48L950ZWT_FREERTOS. I follow the exact same steps as mentioned in the help file, but just a small change in VIM RAM column, instead of of vPreemptiveTick , I have used vPortPreemptiveTick. The former gave me linking errors.

Also, I was getting a error for all the header files included. The error stated that the source files cannot be found. I just added this in all the #include statements to remove this error.

#include "../include/file_name.h" instead of just #include "file_name.h".

That got rid of the compile and linking errors and I was able to generate the executable.

I load the .out file on the board using nowFlashWin.

I am attaching my workspace here. If somebody can tell me where am I going wrong. Are there any project properties to be changed in Code Composer Studio?

It would be great if anybody could share their working FreeRTOS working directory for the RM48 HDK it would be great.

Here is my FreeRTOS workspace

(Please visit the site to view this file)

problems using TMS570LS3117 with Keil with RTX kernel

Somnus Wang — Mon, 20 May 2013 07:00:48 GMT

Hello, I'm using TMS570LS3117 demo board with Keil with RTX kernel. I created a simple project in which I created two tasks.

Then I downloaded this programand and run it. Keil MDK shows that the os_idle_demon task has an error of stack overflow and the program runs out of control.

My MDK version is 4.23 and I used startup_TMS570LS.s provided by Keil. I'm on line waiting for someone help me solving this problem. Hoping for your help.

FLASH Memory Write/Erase Cycles

David Rodriguez Rodriguez — Mon, 20 May 2013 21:29:46 GMT

I am using the microcontroller TMS570LS3137 and F021 API (version -> 1.51) to perform read and write operations on flash memory.

I need to know what would happen if I try to write in Flash memory (program or data Flash) when their write cycles are over.

What would be the return value of the function Fapi_checkFsmForReady () or what would happen if Fapi_issueProgrammingCommand(…) function is called when write cycles are over during writing process?

I would appreciate so much if someone can help me, please.

Regards…

ESM Group 3 error

Alan Thieman — Thu, 16 May 2013 13:16:06 GMT

I have an application that uses the TMS570LS3137 processor. The HET 1 module is used to produce several PWMs The HET2 module also produces a PWM at a different frequency. The ADCs are triggered by RTI 0 interrupt. I recently changed the main timing loop interrupt. It used to be triggered by RTI 1. Now I am having the HET module trigger the main CPU timing loop by having the HET "CNT" instruction trigger the interrupt; I am no longer using (RTI 1).

This all seems to work, but now I am getting ESM group3 errors during power-up.

Can you give a suggestion what I should look for to fix this error?

TPS65381 Wake Up

Rustin Schroeder — Mon, 20 May 2013 19:34:54 GMT

Is there any method on the TPS65381-Q1 for controlling whether or not the PMIC can be woken up by the CANWU pin (e.g. register setting, etc.)? From what I’ve seen in the datasheet, it looks like it is always going to wake up from either source. We have CAN transceivers on our design and intend to have the option of waking the system via CAN wake-up, but would like the option of whether or not it is enforced. Can this be done in the TPS65381-Q1 or must there be some external mechanism for controlling it? If external, any ideas on how to implement?

how received all dcan message identifier number from one message box or whitout message boxs.

Halil Ibrahim — Fri, 17 May 2013 06:51:36 GMT

Hi,

I want to receieved 43 can message with tms570LS31xhdk. I dont want to using all message box. how received all dcan message identifier number from one message box or whitout message boxs.

Thanks.

What should be the value of ATCMRW Bit in Secondary Auxiliary Control Register of Cortex-R4 Core?

Pashan None — Mon, 20 May 2013 14:27:27 GMT

Hello Support,

I find that BTCMRW Bit of Secondary Auxiliary Control register is mentioned in TRM for ECC Check within BTCM Port [RAM] as shown below in the Picture.

I couldn't find anything similar about ATCMRW Bit, even though it is also 64-Bit ECC.

Does this mean ATCMRW Bit is DONT'CARE for all the use cases, especially during Flash Programming?

We need to enable run-time ECC Check for ATCM Port also.

Any infor related to ATCMRW Bit setting will help us understanding it better.

Either TMS570LS3137 or TMS570LS0432 is fine.

Thank You.
Regards
Pashan

RM48L952 stm problem

Peter Begella — Mon, 13 May 2013 10:34:34 GMT

Hi,

I do not know whether this is a known bug or not, but I could not found the issue in the errata. We are using RM48 for one of our projects and we found something interesting.
Circumstances:

- The code is running from the internal flash and we are using an external SDRAM through EMIF. .bss and .data are located here.
- 1 timer and an USB interrupt is used. ( USB host MST )
- Most of the time the problem occurs during an USB read ( Reading data from MST )
- The PLL is running on 200MHz and the VCLK is 100MHz
- We have a small OS which is running on several system without any problem.
- We are using CCS 5.2 and compiler version 4.9.1

The OS context switch part looks like this:

- stmdb sp!,{r4-r11,lr} ; save registers

...

- ldmia sp!,{r4-r11,pc} ; restore registers

As you can see we store r4-r11 and r14 on the stack using STM instruction but sometimes we can see that the last two registers are swapped, so instead of seeing r4-r10, r11, lr we can see r4-r10, lr, r11 on the stack, as a consequence when registers are read back from the stack (which is done by LDM for r4-r11,pc) the system causes a prefetch abort as r11 will be placed to PC.

After a short analysis we have found that if we split STM to 2-3 groups (e.g.: STMDB sp!,{r11,lr); STMDB sp!,{r8-r10}; STMDB sp!,{r4-r7}) then it works perfectly and the problem never occurs. Strangely none of the compiled codes by CodeComposer uses STM for more than 6 registers in one go. Is it possible that using more than 6 register could cause some trouble?
I tried to add a debug code to catch the problem:

test_smtdb:
 .asmfunc

start:
 mov sp,#0x80000000
 orr sp,sp,#0x6000
 mov r0,#1
 mov r1,#2
 mov r3,#4
 mov r4,#5
 mov r5,#6
 mov r6,#7
 mov r7,#8
 mov r8,#9
 mov r9,#10
 mov r10,#11
 mov r11,#12
 mov r12,#13
start2:
 mov r2,#3
 stmdb sp!,{r0-r12,lr} ; save registers
 mov r0,#0
 mov r1,#0
 mov r2,#0
 mov r3,#0
 mov r4,#0
 mov r5,#0
 mov r6,#0
 mov r7,#0
 mov r8,#0
 mov r9,#0
 mov r10,#0
 mov r11,#0
 mov r12,#0
 ldmia sp!,{r0-r12,lr} ; restore registers
 cmp r0,#1
 bne error_func
 cmp r1,#2
 bne error_func
 cmp r2,#3
 bne error_func
 cmp r3,#4
 bne error_func
 cmp r4,#5
 bne error_func
 cmp r5,#6
 bne error_func
 cmp r6,#7
 bne error_func
 cmp r7,#8
 bne error_func
 cmp r8,#9
 bne error_func
 cmp r9,#10
 bne error_func
 cmp r10,#11
 bne error_func
 cmp r11,#12
 bne error_func
 cmp r12,#13
 bne error_func
 mov r2,#0x80000000
 orr r2,r2,#0x2100
 cmp sp,r2
 blt start
 b start2
 mov pc,lr

After startup this code is executed only. In this case there is no USB interrupt just the timer interrupt, but no prefetch problem occurs.

Do you have any suggestions what and where to check?

Thank you in advance!

Kind Regards,
Peter Begella

Update:

- Moving .bss section into the internal RAM solves the problem or at least hides it. But this is not an option for us.

JTAG error: Unable to access the DAP

Michal Sojka — Mon, 13 May 2013 12:25:53 GMT

Dear Sir/Madam!

We experience strange problems with JTAG on TMS570LS3137. After executing our code that was supposed to initialize CAN interface, we were no longer able to use JTAG to work with the CPU. In CCS 5.3.0, we get the following error (we use XDS100v2 emulator):

CortexR4: Error connecting to the target: (Error -1206 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation
package 5.0.872.0)

When we run Target Configurations -> TMS570LS3137.ccxml -> Test Connection, no error is reported (see the log at the end of this message).

Do you have any idea what could have happened to the CPU? Can it be that JTAG security module (AJSM) got incidentally activated?

Additional information:

The problem is reproducible. We "damaged" two boards this way.
JTAG broke when our code was executed/debugged, not during FLASH programming. We successfully loaded the program (to one board with CSS, to the second board with UniFlash tool). Then we used CCS to step through the program, which was the last thing done with the board.
The code was not compiled by CCS, we used the GCC compiler shipped with http://www.arccore.com/products/arctic-studio/.
We tried OpenOCD to communicate with the board - it get into an infinite loop somewhere in the ARM target handling code. No meaningful error was produced by OpenOCD.

Best regards,
-Michal Sojka

Test connection log:

[Start]
Execute the command:
%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
[Result]
-----[Print the board config pathname(s)]------------------------------------
C:\Users\Leos\AppData\Local\.TI\693494126\
0\0\BrdDat\testBoard.dat
-----[Print the reset-command software log-file]-----------------------------
This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'Oct 3 2012'.
The library build time was '21:58:41'.
The library package version is '5.0.872.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.
-----[Print the reset-command hardware log-file]-----------------------------
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).
-----[The log-file for the JTAG TCLK output generated from the PLL]----------
There is no hardware for programming the JTAG TCLK frequency.
-----[Measure the source and frequency of the final JTAG TCLKR input]--------
There is no hardware for measuring the JTAG TCLK frequency.
-----[Perform the standard path-length test on the JTAG IR and DR]-----------
This path-length test uses blocks of 512 32-bit words.
The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 6 bits.
The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.
-----[Perform the Integrity scan-test on the JTAG IR]------------------------
This test will use blocks of 512 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG IR Integrity scan-test has succeeded.
-----[Perform the Integrity scan-test on the JTAG DR]------------------------
This test will use blocks of 512 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG DR Integrity scan-test has succeeded.
[End]

TMS570LS0432 _undefined istruction triggered entering into interrupt routine

Claudio Brandi — Sat, 18 May 2013 14:35:39 GMT

Hi all,

I am using the TMS570LS0432 evaluation board. I am trying to use the SCI serial comunication peripheral in interrupt mode, but I have a problem when the interrup

routine sciHighLevelInterrupt is triggered.

Entering in this routine a precompiled instruction (FMXR) is executed, causing a jump to the _undefined instruction into the Interrupt vector routine.

The execution remain there in a infinite loop because the undefine handler is disabled.

I read in a forum thread that another guy had the same problem but with another processor type (TMS570LS2016).

The Ti support analysis and the relevant suggestion is reported below in red:

The problem ending up in _undefined or _prefetchAbort is,

that you use a library which supports the device floating-point (FPU),

but your code does not enable the FPU.

At the beginning of an interrupt routine a write to the FPU happens,

which causes the _undefined or _prefetchAbort,

if the FPU is disabled The easiest way to fix the issue

is to enable the FPU by calling the

following function at the beginning of _c_int00() in sys_startup..

;-------------------------------------------------------------------------------

; Enable VFP Unit

.def _coreEnableVfp_

.asmfunc

_coreEnableVfp_

mrc p15, #0x00, r0, c1, c0, #0x02

orr r0, r0, #0xF00000

mcr p15, #0x00, r0, c1, c0, #0x02

mov r0, #0x40000000

fmxr fpexc, r0

bx lr

.endasmfunc

I am using the --Float_Support VFPv3D16 and I tryed to insert the suggested routine into my source code but the problem is still present.

When the CPU executes the fmxr fpexc, r0 instruction , the _undefined is triggered again.

Please could I have any further suggestion to fix my Issue ?

Thanks in advance for your support.

Best regards

Claudio

TMS570LS1227 examples?

Calum Mackinnon — Sun, 19 May 2013 15:40:26 GMT

I have installed Hercules MotorWare and CCS from the DRV8301-LS12-KIT. The kit is for the TMS570LS1227. It include examples, but only for the RM46 and RM48. No examples for the TMS570LS1227 or TMS570LS3127. Where can I get the examples for the chip on the kits PCB (i.e. TMS570LS1227)?

Help getting started with the DRV8301-LS12-KIT Motor Dev Kit (TMS570LS1227 processor)

Michael Holmes — Sat, 18 May 2013 17:14:18 GMT

Hi,

I just got a DRV8301_LS12_KIT with the Hercules TMS570LS1227 processor. I want to just spin the motor first. InstaSPIN demo sounded great, but is not living up to the name for me. The written instructions pointed me to ...

Start->Texas Instruments->Hercules->Motor Demos

but all I see are demos for the RM46 & 48 (no demos for the TMS570 processors)

Any suggestions on getting a quick demo to spin the motor would be appreciated!

Also pointers or tips on building the projects (my first attempted ended in a "Can't find 'make'" error).

There's a lot of docs and info, so any help zeroing in on the more useful stuff would be appreciated!!

Again, I'm using the motor kit with the TSM570LS1227 processor.

Thanks in advance,

Mike

Buffered digital output.

matteo lucarelli — Mon, 13 May 2013 15:29:06 GMT

Hi,

I'm working with a TMDX570LS32HDK.

For an ADC app I need to generate a digital waves pattern to feed ad setup my source. My digital pattern is constant through cycles of a single run but is NOT constant from an execution to another. It is someway similar to a serial signal but involves more signals. The pattern cannot be programmed and compiled on code generation because requires to be modified runtime.

The stardand way to generate a similar pattern would be a buffered digital output, where the application can fill the buffer and then start emitting cycling through the buffer at a predefined frequency. Every buffer bit is assigned to the state of a digital output pin.

Which is the bes way to achieve this?

There's somewhere an example to start with?

Thank you,

Matteo

MibSPI rx DMA

Jack Andrews — Tue, 14 May 2013 15:50:02 GMT

Hi,

I'm having trouble using DMA to read MibSPI rx buffers. Attached is my current code:(Please visit the site to view this file)

Here is a screenshot after transfer is complete:

Esentially, two 16 bit bytes have been received: 0x0FFF and 0x0D4A. Note that the memory view on the right shows the mibSPI1 RX buffer. RX_DATA, which uses DMA to transfer from mibSPI RAM to RAM, (see value in watch) is missing the second byte, whilst RX_DATA2 (which uses mibspiGetData() as in the mibSPI example code) contains the correct two bytes as confirmed with a scope. So, the SPI is working, but DMA copy to RAM is not.

Please take a look at my code and see if anything is wrong. Also, I have a question - what is the function of R(T)XDMA_MAPx? I thought MIBSPI[1] request source is hardwired to DMAREQ[0]?

RM42 SPI bootloader, unresolved symbol "api_load"

mikkel johnsen — Fri, 17 May 2013 10:06:34 GMT

I'm trying to get a SPI Bootloader example up and running on my Hercules RM42 HDK. More specifically I've downloaded the SafetyMCU_Bootloader_v1.2.0.zip file and am trying to run the project contained in "./SafetyMCU_Bootloader/RM42/boot_spi"

My problem is this: When trying to build the RM42 project, I end up with a few linker errors:

"unresolved symbol api_load, first referenced in ./src/sys_core.obj"
"unresolved symbol api_run, first referenced in ./src/sys_core.obj"
"unresolved symbol api_size, first referenced in ./src/sys_core.obj"

The reference is from this snippet of ./src/sys_core.asm :

;-------------------------------------------------------------------------------
;
; Copy the Flash API from flash to SRAM.
;

.def _copyAPI2RAM_
.asmfunc

_copyAPI2RAM_

.ref api_load
flash_load .word api_load
.ref api_run
flash_run .word api_run
.ref api_size
flash_size .word api_size

ldr r0, flash_load
ldr r1, flash_run
ldr r2, flash_size
add r2, r1, r2
copy_loop1:
ldr r3, [r0], #4
str r3, [r1], #4
cmp r1, r2
blt copy_loop1
bx lr

.endasmfunc

I am linking to the following files in my project:

rtsv7R4_A_le_eabi.lib
F021_API_CortexR4_LE_v3D16.lib
libc.a

Can anyone help me get past this problem ? :)

I am compiling on a Windows 7 64bit, using CCS 5.4, F021 flash API 1.51.0.

emac receive only broadcast packets - RM4 HDK

Tomasz Chalupka — Fri, 17 May 2013 11:45:27 GMT

I can't receive any unicast packets through emac in my RM48L950 (HDK)
When I send broadcast packets to it everything is ok, when sending unicast RX interrupt doesn't get active.

I have emac initialisation routine similar to lwIP for RM48 HDK. I'm using channel 0. What I do:

mymac[] = {0xaa,0xbb,0xcc,0xcc,0xbb,0xaa}
EMACInit()
MDIOInit()
EMACRxUnicastSet()
EMACBroadCastEnable()
EMACMACSrcAddrSet() // set mymac
for all 8 channels {
EMACMACArrdSet() // set mymac and EMAC_MACADDR_MATCH
EMACRxHdrDescPtrWrite() // set null to HDP
EMACTxHdrDescPtrWrite() // set null to HDP
}
... link setup ...
EMACCoreIntAck() //rx interrupt
EMACCoreIntAck() //tx interrupt

EMACNumFreeBufSet()

EMACTxEnable()
EMACRxEnable()

EMACRxHdrDescPtrWrite() // set correct hdp in CPPI

EMACMIIEnable()

EMACTxIntPulseEnable()
EMACRxIntPulseEnable()

When I receive packet from RM4 on my PC (e.g. answer for arp-request) it contains correct mac (source mac is "mymac").

EMAC registers from debug:
MACSRCADDRLO = 0x0000AABB
MACSRCADDRHI = 0x00000000 // why not 0xCCCCBBAA ?

MACADDRLO and MACADDRHI have "unable to read" error

Interrupts during flash write

Richard Burke — Wed, 16 May 2012 10:36:01 GMT

Hello,

My understanding is that with the F035 flash library (as used on the TMS570LS20216 for example), interrupts must be disabled during flash write.

Are there any restrictions for the F021 flash library (as used on the TMS570LS2124 for example)?

Thanks,

Richard

MIBSPI with DMA triggered from two tasks

Masayuki MIYOSHI — Fri, 26 Apr 2013 06:03:41 GMT

Hello,

I am trying to check the MIBSPI and DMA function on TMS570LS3137 device.

On my board MIBSPI1, two slaves are connected.
And my RTOS generates two periodic tasks (1ms task and 10ms task).

Now, I would like to carry out SPI communication with SLAVE1 by 1ms task,

andwith SLAVE2 by 10ms task.

Furthermore, in order to reduce the overhead of CPU,
I would like to use RX DMA and TX DMA with MIBSPI1.

The conditions of MIBSPI1 communication are as follows.

"MASTER(TMS570) <-> SLAVE1"

Communication cycle : 1ms (SPI is triggered by 1ms task)
The number of data transmission at 1 cycle : 1 to 100 words.

(The number is variable and it may change for every cycle. It is decided in the 1ms task).

Word length : 32bits
Baudrate : 5MHz
Chip select : CS_0

"MASTER(TMS570) <-> SLAVE2"

Communication cycle : 10ms (SPI is triggered by 10ms task)
The number of data transmission at 1 cycle : 1 to 100 words.

(The number is variable and it may change for every cycle. It is decided in the 10ms task).

Chip select : CS_1

Others are the same conditions as SLAVE1.

The priority of SLAVE1 is higher than SLAVE2, and the communication with SLAVE2 can be interrupted

by the communication with SLAVE1.

I think there are three points which make the problem not easy.

1. The number of data transmission is variable for every cycle.

2. In the worst case, the send data size is over MIBRAM size.
(There are 128 buffers in MIBRAM, and one buffer can contain 16bits data for each of transmit and receive.
so MIBRAM can contain up to 2048 bits transmit/receive data .

However, I would like to send 3200 bits (32-bit * 100-word) data in the case of maximum transmission. )

3. Cooperation with TX/RX DMA.

Could you please tell me how it can be resolved?

ESM Error on TMDXRM48HDK

Jamie Wardlaw — Fri, 17 May 2013 17:39:22 GMT

Hello,

I recently received a new TMDXRM48HDK for continued prototype development (our previous HDK was broken during testing).

The application that was previously working on our other HDK throws ESM errors on the new board. The new board has never been tested with external IO (source of previous failure). I am seeing intermittent success with running the board with the application we developed, also with the demo applications that come with the HDK.

To try and debug the problem I have tried to generate from HALcogen empty applications with only the GIO enabled and toggle the NHET pins in the main loop. This has had intermittent success, with ESM errors occurring frequently. If I do anything more advanced such as enabling a HET driver and trying to both PWM a HET pin and, say, use another as GIO I end up with ESM errors.

Can anyone help me debug the source of the ESM error in the event there is a chance it could be an initialization issue with the micro? I think it is unlikely and we may have been shipped a defective board.

Thanks

Jamie

DCAN IFxCMD Register Usage related to Clearing of IntPnd and NewDat bits of CAN Receive Message Objects

Pashan — Thu, 21 Oct 2010 02:06:13 GMT

Hello,

By setting HIGH only Bits 19, 18 and programming correct Message Number bits [7-0] of IFxCMD Register within DCAN, is it possible to clear the IntPnd and NewDat bits of the respective CAN Receive Message Object?

Or, do I have to set Bits 22, 21 and 20 also within IFxCMD Register before writing Message Number field for clearing the IntPnd and NewDat bits for CAN Receive Message Objects?

Thank you.

Regards

Pashan

Configure ADC samples and ADC calibration

David Rodriguez Rodriguez — Fri, 17 May 2013 00:46:29 GMT

I am using the microcontroller TMS570LS3137, I don´t know if it is possible to configure a number of samples of the ADC before enable interrupt, in order to perform a more reliable conversion.

My setup is:

12 bit resolution

Single conversion

If that is possible, what are the registers that I should set?

I did not find related information on specific datasheet.

Another question is, What is the correct sequence for a best ADC calibration?

I would appreciate so much if someone can help me, please.

Regards…

CAN Messages with multiple Signals

ishan maniar — Thu, 16 May 2013 09:40:16 GMT

Hie,

I am using the TMS57031x HDK.

For example,

I am sending a Message with an ID 0x60 and DLC 8. But this Message contains multiple signals i.e 8 different signals each 1 byte long in Message with ID 0x60. so I would be sending signals separately.

Take the Message Structure:

Message ID 0x60

DLC 8:

MSG_1-> bit 0 to bit 8

MSG_2-> 9:16

MSG_3-> 17:24

MSG_4-> 25:32

MSG_5-> 33-40

MSG_6 -> 41:48

MSG_7-> 49:56

MSG_8 -> 57:64

I.e the Above are the signals in the Message bit length as mentioned

I would like to know if it would be possible to mention this in the Halcogen?

If Not in halcogen, would it be possible to include it in the Driver code.

Awaiting your Reply

Regards,

Ishan Maniar

Where are the pins? (MibSpi in parallel 8 mode on TMS570)

matteo lucarelli — Thu, 16 May 2013 14:53:54 GMT

Hi,

I'm working on a TMDX570LS31HDK. Multi buffered SPI (MibSPI5) can be used in parallel 8 mode so the ouput should use 8 pins for SOMI lines 0 to 7.

In HalCoGe (in the MibSPI5 and in mux tabs) and in the user manual pin description there are SOMI lines only from 0 to 3.

Where are the others?

Can the TMDX570LS31HDK use 8 parallel mode or this is reserved to other HW models?

Grazie,

Matteo

PMIC (TPS65381-Q1) and MCU (RM48L950)

Rustin Schroeder — Mon, 06 May 2013 20:10:15 GMT

I am a bit confused on what to do in terms of an external pull resistor on the ERROR/WDI and nERROR pins of the PMIC (TPS65381-Q1) and MCU (RM48L950). The TPS65381-Q1 datasheet describes two modes of operation: TMS570 mode and PWM mode. If using TMS570 mode, it describes an error condition being detected when the ERROR/WDI pin remains low for a programmed amount of time. This almost makes it sound like a pull-up should be used.

The RM48L950 datasheet shows the default pin state for nERROR is a 20uA pull-down, which contradicts my assumption above. Lastly, the RM48 HDK schematic on Page 7 shows a 1K pull-up on nERROR through an LED, which seems like it would support my initial assumption but contradict the default pull-down state for the nERROR pin. So, if adding an external pull device, should it be pull-up or pull-down…or could it be either and why?