TCRAM Wrapper Control and Status Registers

The RAM wrapper register structure is defined as follows (in system.h in the TI Demo Software that comes with the TMS570 development stick):

(big endian version)

struct ramW
{
    unsigned CTRL;              /* 0x0000 */
    unsigned       : 16U;       /* 0x0004 */
    unsigned THRES : 16U;       /* 0x0004 */
    unsigned       : 16U;       /* 0x0008 */
    unsigned OCCUR : 16U;       /* 0x0008 */
    unsigned         : 31U;     /* 0x000C */
    unsigned INTCTRL :  1U;     /* 0x000C */
    unsigned           : 16U;   /* 0x0010 */
    unsigned ERRSTATUS : 16U;   /* 0x0010 */
    unsigned          : 14U;    /* 0x0014 */
    unsigned SERRADDR : 15U;    /* 0x0014 */
    unsigned          :  3U;    /* 0x0014 */
    unsigned : 32U;             /* 0x0018 */
    unsigned          :  9U;    /* 0x001C */
    unsigned UERRADDR : 20U;    /* 0x001C */
    unsigned          :  3U;    /* 0x001C */
    unsigned : 32U;             /* 0x0020 */
    unsigned : 32U;             /* 0x0024 */
    unsigned : 32U;             /* 0x0028 */
    unsigned      : 16U;        /* 0x0030 */
    unsigned TEST : 16U;        /* 0x0030 */
    unsigned : 32U;             /* 0x0034 */
    unsigned ADDRDECU;          /* 0x0038 */
    unsigned          :  9U;    /* 0x003C */
    unsigned PERRADDR : 20U;    /* 0x003C */
    unsigned          :  3U;    /* 0x003C */
};

The TEST register is commented as address offset 0x30, which agrees with the Technical Reference Manual, but in the code snippet above, from system.h, there is no entry at address offset 0x2C, therefore the TEST register will be at offset 0x2C. Can anyone confirm that this is a mistake, and that there should be another entry of......
    unsigned : 32U;             /* 0x002C */

between:
unsigned : 32U;             /* 0x0028 */

and
unsigned      : 16U;        /* 0x0030 */

regards,
Dave