I am including this question from a recent customer email as it comes up occasionally with the legacy TMS570LS20216S FMEDA document. In this document, we provide FIT rates for the die, but not for the package.
"How do I estimate package failure rate for the product if the FIT rates shown are only for the die?"
Package FIT rate is most often estimated using a standard such as IEC TR62380. Based on the package type (QFP, BGA, ...), usage profile (# of temp cycles per year, temperature variation between off and on states, etc), # of pins, and size of the package it is possible to use such a standard to estimate FIT rate. For example, if I use this standard and the typical automotive usage profiles given, the raw FIT rate of the 144 QFP is roughly 290 FIT and the 337 BGA is roughly 275 FIT.
These numbers could be de-rated depending on the number of pins/balls used in your application for safety critical function. You could also choose to split the failure rate to an average per pin and consider the failure rate per pin, per safety function. There are many different strategies here which can be argued. What is critical is to ensure that all of the ICs on your PCB use the same estimation method and apply a consistent usage profile which is relevant to your end equipment.
Note that the numbers in this standard are very conservative. The TI early failure rate studies and field data indicate the intrinsic package fit of both packages is roughly 0 FIT in automotive use conditions and product lifetimes. As with all reliability estimation standards, there is not a clear distinction between intrinsic failure rate (random failure rate) and failure rate due to systematic issues. At least for packaging, the FIT rates seen in field are dominated by systematic issues.
how would you balance the FIT rates among package and chip ? Does your field experience for the chip show only slight difference between field failure rates and estimated failure rates or are they similar different like in your example (IEC TR 62380 estimate roughly 300FIT while field experience is nearly 0 FIT) ?
IEC TR 62380 often assignes nearly 95% of the failure rates to the package, while another manufacturer assignes e.g. 75% failure rates to the chip and only 25% to the package.
The data available to me indicates that IEC 62380 is at least 2 orders of magnitude pessimistic for package FIT and at least one order of magnitude pessimistic for permanent fit of silicon. IEC 62380 also does not model transient FIT of silicon due to soft error, which by my data is the dominant failure mode by over two orders of magnitude on most devices.
In my opinion, the big issue is the identification of systematic vs. random failures. You need a very large amount of data on a particular product to determine whether a problem is truly systematic or random. Without adequate sample size and successful root cause analysis, the tendency is to lump unexplained failures as random. Some of the more aggressive papers in the semiconductor reliability arena would argue that there are no truly random permanent failures.
I am not sure that a generalized statement on package FIT vs. die permanent FIT can be made. Field and EFR data available to me indicates that both are near zero for our product, with transient FIT due to soft error becoming the primary concern. The die seems to be more significant than package. This is based on TI digital products at 130nm and smaller geometries in automotive applications. Other products, applications, or suppliers may have data which indicates different results.
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