Hello,
I'd like to verify the RAM ECC functionality, I'm calling
_memoryInit_();
_coreEnableRamEcc_();
but, the system gets stuck during _memoryInit_ call.
Is there is a workaround for this issue?
Thank you
Vaclav
P.S. I'm using RM48L950, HALCoGen 3.0
Hello Vaclav,
Which board are you using, TMS570LS3x HDK or RM48 HDK?
For RM48 HDK, you can not init FlexRya RAM. Can you try this value 0x1C57F for ramIniMask in sys_memory.asm
Regards,
QJ
I have RM48 HDK, your proposal works, I had there 0x1E57F instead.
In fact, I'd like to ask you one more question regarding the RAM ECC test. So, the test is started now, but after checking the single error status, the system gets stuck again
if (!((tcram1REG->RAMERRSTATUS & 1) || (tcram2REG->RAMERRSTATUS & 1))) {
... it ends up here and then gets stuck ...
}
Do you have any hint why is doing so?
Are you running the RAM ECC check routine as shown in the example code that comes with SPNA106A? Can you post your entire RAM ECC check routine?
Regards, Sunil
Hello Sunil,
I'm using the routine originating form the SPNA106A example code ...
----
void checkB0RAMECC(void){ volatile unsigned int ramread = 0; tcram1REG->RAMCTRL = 0x0005010A; // enable writes to ECC RAM, enable ECC error response tcram2REG->RAMCTRL = 0x0005010A; tcram1REG->RAMTHRESHOLD = 0x1; // the first 1-bit error will cause an error response tcram2REG->RAMTHRESHOLD = 0x1; tcram1REG->RAMINTCTRL = 0x1; // allow SERR to be reported to ESM tcram2REG->RAMINTCTRL = 0x1; tcramA1bitError ^= 0x1; // cause a 1-bit ECC error tcram1REG->RAMCTRL = 0x0005000A; // disable writes to ECC RAM tcram2REG->RAMCTRL = 0x0005000A; ramread = tcramA1bit; // read from location with 1-bit ECC error if (!((tcram1REG->RAMERRSTATUS & 1) || (tcram2REG->RAMERRSTATUS & 1))) // SERR not set in TCRAM1 or TCRAM2 modules { tcramClass2Error(); // TCRAM module does not reflect 1-bit error reported by CPU } else { tcram1REG->RAMERRSTATUS = 0x1; // clear SERR flag tcram2REG->RAMERRSTATUS = 0x1; esmREG->ESTATUS1[0] = 0x14000000; // clear status flags for ESM group1 channels 26 and 28 } tcram1REG->RAMCTRL = 0x0005010A; // enable writes to ECC RAM, enable ECC error response tcram2REG->RAMCTRL = 0x0005010A; tcramA2bitError ^= 0x3; // cause a 2-bit ECC error ramread = tcram1REG->RAMCTRL; ramread = tcram2REG->RAMCTRL; ramread = tcramA2bit; // read from location with 2-bit ECC error // this will cause a data abort to be generated}
Can you check if there is any other bit getting set in the RAM ERR STATUS register? You can also check if the RAM OCCUR register increments to indicate that a single-bit error was reported by the CPU's ECC logic.
If you are using CCS for the debug, you can also view CPU registers, including the co-processor registers. You can check the Correctable Fault Location Register. This register contains a bit to indicate that a single-bit TCM ECC error was detected.
Thank you for your feedback. The test works now, the problem was in ECC enable assembler sequence.
Regards Vaclav
Did you mean the ECC enable sequence used in the example initialization code?
Hallo Sunil,
No, in fact, the one used in the example showing initialization code is correct. The mistake was on my side.
Dear TI experts,I have similar issue with simple blinky example in IAR environment. The code of sys_memory.asm compiled and linked by IAR EWARM works incorrectly - processor stays in mloop.IAR EWARM installation: IAR Assembler for ARM 6.40.2.53884 (6.40.2.53884) IAR C/C++ Compiler for ARM 6.40.2.23884 (6.40.2.23884) IAR ELF Linker for ARM 6.40.2.53884 (6.40.2.53884)target: TMS570LS3x HDKcode snippet:;-------------------------------------------------------------------------------; Initialize memory PUBLIC _memoryInit__memoryInit_ ldr r12, regMinitGcr ; MINITGCR register pointer mov r4, #0xA str r4, [r12] ldr r4, ramInitMask ; load RAM initialization mask str r4, [r12, #4]mloop ldr r5, [r12, #12] tst r5, #0x100 beq mloop mov r4, #5 str r4, [r12] bx lrramInitMask dcd 0x657F ; value copied from CCS project regMinitGcr dcd 0xFFFFFF5CA program built by TMS470 Code Generation Tools 4.9.1 is running properly, does not get stuck in _memoryInit_ function. By the way, the function _coreEnableRamEcc_() is not called.IAR and TI compilers produce a different object code:tst r5, #0x100
E3150F40 (IAR EWARM)
E3150C01 (CCSv5)Dump of SYS1 registers in IAR debugger: MINITGCR = 0xA MSINENA = 0x657F MSTCGSTAT = 0x0 (0x100 expected)Please do you have any idea what could be wrong?Many thanks in advance,CheersJiri
FYI
This topic has been re-issued in this forum post
http://e2e.ti.com/support/microcontrollers/hercules/f/312/p/205959/731575.aspx#731575
hi,i am using RM48L950 MDK ,for our development,do you have any RM48L950 MDK examples OR library function?
thank you !
Hello Marlon,
have you checked some of following pages? RM4 processor is based on the same core ( Lockstep Dual Cortex-R4F) as the TMS570 processor is, so you can also utilize examples originally given for TMS570.
RM4 ARM Cortex-R4F Series http://www.ti.com/mcu/docs/mcuprodtoolsw.tsp?sectionId=95&tabId=2843&familyId=2056&toolTypeId=1
Hercules Platform Overview http://processors.wiki.ti.com/index.php/Category:Hercules
Hecules TMS570 Safety MCU Example Code wiki http://processors.wiki.ti.com/index.php/Category:HerculesSWExamples
Nevetheless, this forum thread has been already "closed" (the answer was verified), so I would recommend you to submit a new post for further support by TI experts.
Good luck & cheers, Jiri