What is the side-effect of accessing/modifying Transfer RAM of MibSPI in Muti-Buffer Mode belonging to a currently non-active Transfer Group when a particular Transfer Group is active sending data over SPI at a paricular instant of time?
Is it a requirement that CPU/DMA should not access/modify Transfer RAM of MibSPI in any way when any of the available Transfer Group is active transferring data using SPI Bus? or it doesn't not matter as long as the active Transfer RAM is untocuhed by CPU/DMA.
Any info will help me a lot to understand Transfer Group activity.
This is a advanced question. I will forward your question to our SPI expert.
Internally, MIBSPI will read a TXRAM location whenever it’s supposed to transfer a data.
At the end of a transfer, the RX data will be copied to the RXRAM. Typically, the arbitration scheme is,
There are two possibilities.
FSM access will be stalled till VBUSP access completes.
Overall, there should not be any functional issues. But, the # of cycles might vary if there are a lot of VBUSP accesses to MibRAM during Transfer Group transactions.
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