MibSPI RAM Access during Transfer Group being active

This question is answered

Posted by Pashan None

on Mar 16 2012 17:08 PM

Genius3490 points

Hello Support,

What is the side-effect of accessing/modifying Transfer RAM of MibSPI in Muti-Buffer Mode belonging to a currently non-active Transfer Group when a particular Transfer Group is active sending data over SPI at a paricular instant of time?

Is it a requirement that CPU/DMA should not access/modify Transfer RAM of MibSPI in any way when any of the available Transfer Group is active transferring data using SPI Bus? or it doesn't not matter as long as the active Transfer RAM is untocuhed by CPU/DMA.

Any info will help me a lot to understand Transfer Group activity.

Thank you.

Regards

Pashan

All Replies

Posted by Haixiao Weng

on Mar 16 2012 20:14 PM

Genius9955 points

This is a advanced question. I will forward your question to our SPI expert.

Regards,

Haixiao

Posted by Prathap

on Apr 03 2012 00:24 AM

Verified Answer

Verified by Pashan None

Expert6465 points

Hi Pashan

Internally, MIBSPI will read a TXRAM location whenever it’s supposed to transfer a data.

At the end of a transfer, the RX data will be copied to the RXRAM. Typically, the arbitration scheme is,

If both VBUSP( User write) access and MIBSPI FSM( Module ) access Mib RAM at the same time, then FSM will take priority
If either of them is already accessing, then the other access will wait.

There are two possibilities.

When FSM tries to access MibRAM, if a VBUSP port is already accessing the RAM, then

FSM access will be stalled till VBUSP access completes.

Similarly, if FSM is already accessing MIbRAM while VBUSP port tries to access the RAM, it will have to wait.

Overall, there should not be any functional issues. But, the # of cycles might vary if there are a lot of VBUSP accesses to MibRAM during Transfer Group transactions.

Best Regards
Prathap

~~~ If a post answers your question, please mark it with the"Verify Answer" button. ~~~