Could you verify my understanding on the HET program execution of TMS570 below?
1) The HET program starts to be executed on the rising edge of loop resolution clock (LR clock), right?
2) Within each loop resolution period (LRP), each of the HET instructions are executed once by the HET state machine. The flow of execution is determined by the next address and conditional address. Am I right?
3) In Table 18-46 of TMS570 TRM (Page 1326), there is a column called Cycles during which an HET instruction is executed. Does this cycle mean VCLK2 clock or something else (e.g. HR clock or LR clock)? Is the HR clock mainly used to implement the hr_data field for the HR clock delay within one LRP?
4) Pin actions and events become effective on the next rising edge of the LR clock only (instead of VCLK2 or HR clock), right?
Thank you so much.
1] The HET program is executed within a loop resolution. Your assumption is correct.
2] This is correct.
3] The HET is clocked by VCLK2. All instruction cycle are based on VCLK2. Depending on the LR prescaler you will be able to executed more or less instruction. Some instructions have different cycle count depending on condition. It is important to sum up the worst case scenario do define your loop resolution. You want to be sure the HET will be able to execute all instruction in 1 loop resolution. I case of problem there is a flag that will tell you that HET reaches an overrun. (unable to execute all instruction within a loop resolution} The HR clock is used to add more precision. As you said, all pin action are done on a LR resolution. Using HR resolution, it is possible to delay the pin action from a LR resolution to LR + HR resolution.
4] Yes, when HR is not use, all pin action are based on LR.
Please let me know if I've answered all your points.
Thanks and Regards,
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