What is the minimum time that the PORRST line needs to be asserted to ensure that all parts of the TMS570 processor are comfortably in a reset state.?
7.3.1 Timing Requirements For PORRST shows 1ms from the time that VCC crosses VCCPORH and 1ms VCCIO crosses VCCIORH. The figure is found in SPNS141F http://www.ti.com/litv/pdf/spns141f
In this 1ms time will it cover PLL lock time and oscillator setling time.?
Kindly let me know what is the Oscillator setttling time ?
What is the PLL clock lock time...?
Kevin Lavery wrote the following post at Jun 29, 2012 2:07 PM:
The PLL is off by default so your code will enable that; so the PLL is not enabled during that time.
The oscillator typically gets the external crystal started in that 1ms time. However, if the crystal amplitude has not reached a sufficient swing at the end of the 1ms time, there is some additional time (based upon the Low Frequency LPO clock) that the device will wait for the oscillator to start-up. Bottom line, the oscillator start-up is typically completed in this 1ms.
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