DMA seems to auto-initiate in single block transfer mode

I am attempting to use the DMA in single block transfer mode on channel1 to transfer a block of data to the the CRC peripheral using a software trigger.  The behavior I observe is that the following after the registers are configured and the software trigger is written:

SWCHENAS: 0x00000002

PEND: 0x00000002

DMASTAT: 0x00000002

PBACSADDR: 0x000AD3B8

PBACDADDR:  0xFE000060

PBACTC: 0x00010005 (Frame count contains values of 0 and 1, Element count contains values from 0 to A.  The configuration is for a test block containing 10 64 bit elements)

All of the above values look correct for the configuration that I am using.  My expectation is that after a single block transfer (i.e. Frame count =1 and Element count =10) the DMA peripherla should clear the SWCHENAS bit resulting in stopping the channel transfer.  Instead what I see is that the values/conditions above persist and data continues to be transfered tot he CRC peripheral.

Following is the static DMA configuration that I believe to be pertinent to the single block transfer operation that I am attempting to achieve:

GCTRL: 0x00014000

HWCHENAS: 0x00000001

DMACTRLPKT01.ITCOUNT: 0x001000A

DMACTRLPKT01.CHCTRL: 0x0000F119

* Single block transfer mode,
* Constant Addressing mode write,
* Post-increment mode read,
* block transfer (i.e. Frame count * Element Count number of 64 bit values ),
* Write element is double word 64-bit (i.e. CRC PSA_SIGREGL1 length),
* Read element is double word 64-bit (i.e. CRC PSA_SIGREGL1 length),
* No channel chaining
 

Following is the full set of DMACTRLPKT01 values  (Address range  0xFFF80020-0xFFF8003C):

0x000AD3B8

0xFE000060

0x0001000A

0x00000000

0x0000F119

0x00000000

0x00000000

0x000AD3B8

Any suggestions on what could be causing the "auto-initiation" type behavior with this configuration is greatly appreciated.

Thank you,

Jeremy