I am attempting to use the DMA in single block transfer mode on channel1 to transfer a block of data to the the CRC peripheral using a software trigger. The behavior I observe is that the following after the registers are configured and the software trigger is written:
PBACTC: 0x00010005 (Frame count contains values of 0 and 1, Element count contains values from 0 to A. The configuration is for a test block containing 10 64 bit elements)
All of the above values look correct for the configuration that I am using. My expectation is that after a single block transfer (i.e. Frame count =1 and Element count =10) the DMA peripherla should clear the SWCHENAS bit resulting in stopping the channel transfer. Instead what I see is that the values/conditions above persist and data continues to be transfered tot he CRC peripheral.
Following is the static DMA configuration that I believe to be pertinent to the single block transfer operation that I am attempting to achieve:
* Single block transfer mode, * Constant Addressing mode write, * Post-increment mode read, * block transfer (i.e. Frame count * Element Count number of 64 bit values ), * Write element is double word 64-bit (i.e. CRC PSA_SIGREGL1 length),* Read element is double word 64-bit (i.e. CRC PSA_SIGREGL1 length),* No channel chaining
Following is the full set of DMACTRLPKT01 values (Address range 0xFFF80020-0xFFF8003C):
Any suggestions on what could be causing the "auto-initiation" type behavior with this configuration is greatly appreciated.
In your config, I noticed that the AIM bit is set. For software triggered channels with AIM bit set, DMA will continuously perform the transfer.
Can you try with AIM bit = 0 (CHCTRL)?
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