There is a file called sys_core.asm within spna106a.zip archive. [spna106a.pdf]
There is a function called _esmCcmErrorsClear_ within sys_core.asm file.
In that function, there is a WRITE to VIM INTREQ Register.
But according to the TRM, VIM INTREQ is a READONLY Register.
So, is the code wrong or TRM wrong?
The TRM needs to be updated to include the write-clear functionality added to the pending interrupt status register in the VIM. Thanks for identifying this issue with our documentation.
Do I have to clear INTREQ Register within the Interrupt Routine before returning in order to clear the Pending Interrupt Flag?
Please elaborate more on the INTREQ Register usage from end-user perspective because you mentioned that it is WRITE_CLEAR Register.
Under what conditions, end-user must perform WRITE_CLEAR to INTREQ Register?
Any more information will be helpful for debugging my code.
The INTREQ flag gets cleared under either of the following conditions:
INTREQ bit is edge-triggered or Level-Triggered w.r.t. ESM Error Sources [Like Group 2 Bit 2 -- CCM-R4 Compare Error]?
I am assuming Level-Triggered.
If it is Level-Triggered, then once I clear the ESM Group 2 Status Register, then will INTREQ Bit revert back to ZERO state and hence no subsequent FIQ Interrupt?
I am just trying to understand the behaviour.
If the application follows either of the first three methods of servicing the interrupts, the INTREQ flag is automatically cleared and the application does not have to do anything else after that. The INTREQ flag needs to be explicitly cleared only for the case where the application chooses to not use the vectored mode for servicing the interrupt and does the interrupt prioritization completely in software. In this case, it is better for the application to not assume (or care) about whether a particular interrupt is indicated as a pulse or a level to the VIM. It needs to explicitly write-clear the INTREQ just to account for the possibility of a pulse interrupt.
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