What are the available clock sources and domains? What registers are used to map a selected clock source for a particular domain?

 The clock sources and domains are managed by the Global Clock control Module (GCM). The clock domain output signals generated (from the selected clock source input) by the GCM are used to clock the various modules on the device. GCM also controls the enabling and disabling of the clock sources and domains.
 
The following clock sources are available:
- main oscillator clock
- primary PLL output clock (can be a modulated clock)
- low frequency output clock from the internal reference oscillator
- high frequency output clock from the internal reference oscillator
- secondary PLL output clock dedicated for FlexRay  (non-modulated)

These are the clock domains:
- CPU clock domain (GCLK)
- system bus clock domain (HCLK)
- system peripheral clock domain (VCLK_sys)
- peripheral clock domains (VCLK_periph, and VCLK2)
- primary and secondary asynchronous clock domains (AVCLK1, AVCLK2 for DCAN and FlexRay)
- real-time interrupt clock domain (RTICLK1)
  
To map a desired clock source to a clock domain, use the following System registers:
- GHVSRC register for mapping the clock source to GCLK, HCLK, VCLK_sys, VCLK_periph.
- AVCLKSRC register for mapping clock source to AVCLK1, and AVCLK2.
- RCLKSRC register for mapping clock source to RTICLK1 domain. 
 
To enable/disable or check the status of clock sources, use the following System registers:
- CSDIS (Clock Source Disable),
- CSDISSET (Clock Source Disable Set)
- CSDISCLR (Clock Source Disable Clear)
- CSVSTAT (Clock Source Valid Status)

To enable/disable clock domains, use the following System registers:
- CDDIS (Clock Domain Disable)
- CDDISSET (Clock Domain Disable Set)
- CDDISCLR (Clock Domain Disable Clear)

For details on clock source/domain mapping, enable/disable sequencing, clock relationships, frequency restrictions, etc. please refer to the TMS570LS series Technical Reference Manual SPNU489.