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NHET maximum HR clock

Other Parts Discussed in Thread: HALCOGEN, RM48L940

Hi,

I'm working with a RM48HDk and need the maximum performance from one of the HET.

In Halcogen I've set the VCLK2 prescaler to 0 obtaining a HET HR clock of 200MHz.

That's the double of default frequency but my het program works well (and reach the performance I need)

Can this set be dangerous for the HET ?

Grazie,

Matteo

p.s:

This info should be on SPNS174A but for some reason the table on par3.3 is uncomplete. Do the docs has been updated?

  • Matteo,

    You are violating the spec of VCLK. TI cannot guarantee if the device would work correctly in this condition.

    Thanks and regards,

    Zhaohong
  • So which is the maximum frequency?

    I cannot found this information on my datasheet (SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013). There's an updated/corrected version of it?

    Do you think the overclocking could lead to electrical problems or computational only? (in the latter case I don't realy care).

    Thank you

  • It is 100MHz, it should be documented in table 3-1 like you will find it documented for the RM48L940 and other parts, but due to a 'filtering' problem it got filtered out of the PDF that was generated for SPNS174A. Thanks for pointing this out and we'll get it corrected.

    I don't think we can predict what will occur with VCLK running at 2x it's rated speed, because it's not just the N2HET that uses this clock. Quite a lot of the system uses this clock and you might even cause an that ripples back to the CPU.
    On the other hand with just one board you might not see any problem -- but please don't deduce from that it is ok to overclock.
  • Hi and thank you for the reply.

    Perhaps there's a misunderstanding. I'm raising only the the VCLK2 to 200KHz using its prescaler, not the VKLC itself.

    Both on the Datasheet  ("4.6.2.2 Mapping of Clock Domains ti Device Modules") and inside HalCOGen the VCLK2 is reported as used only by NHET/HTU.

    Is that wrong too?

  • Hi Matteo,

    There is another constraint on VCLK2. It must be set as an integer multiple of VCLK. So you can have VCLK=100MHz, VCLK2=100MHz.
    But you can't have VCLK=100MHz, VCLK2=50MHz (no less 200KHz).

    Why did you want to set VCLK2 so low, as opposed to using the HET's LRP and HRP prescalers?
  • Hi Antony,
    perhapes thee's another misundertanding here.
    I'm setting the VCLK2 to 200KHz and leaving the VCLK to 100KHz (the default). Why you say "Why did you want to set VCLK2 so low"? My problem is the opposite.
    Matteo
  • Hi Matteo,

    What he means is, why should you change the VCLK2 value, when you can achieve similar results by changing the HR and LR prescalers and by using HR instructions in your HET program? By using HR instructions, you will be able to achieve higher precision than normal instructions. The best way would be to keep the VCLK2 at 100MHz(within the recommended limit) and just adjusting the HET prescaler values.

    Are you not able to achieve the performance without raising VCLK2? 

    It would also be good if you can share your use-case and the performance you are targetting.

    Regards,

    Vineeth

  • Antony: soory. he error was mine. I wrote KHz but I mean MHz!
  • I'm using the HET to generate 4 square wave having fixed frequency and variable duty. The frequency must be in the order of 400KHz and the duty resolution should be the less as possible (at least 1% but 2% can be accepted.

    I can do this with 5 instruction in the HET code:

    L00 CNT { next=L01,reg=A,max=99};
    L01 MCMP { next=L02,hr_lr=LOW,en_pin_action=ON,pin=1,order=REG_GE_DATA,action=PULSEHI,reg=A,data=50};
    L02 MCMP { next=L03,hr_lr=LOW,en_pin_action=ON,pin=15,order=REG_GE_DATA,action=PULSEHI,reg=A,data=50};
    L03 MCMP { next=L04,hr_lr=LOW,en_pin_action=ON,pin=13,order=REG_GE_DATA,action=PULSEHI,reg=A,data=50};
    L04 MCMP { next=L00,hr_lr=LOW,en_pin_action=ON,pin=5,order=REG_GE_DATA,action=PULSEHI,reg=A,data=50};

    Modifyng the "data" field of the four MCMP I can modify the dutys.
    The "max" field in the CNT intruction gives my duty resolution.

    The output frequency is then VCKL2 / (8*100) where 8 is the cycle count of a single execution and 100 is my duty resolution (the number of execution required for a single square wave).

    Raising the VCLK2 to 200MHz I can generate a ~378KHz wave with ~1.5% duty resolution, wich is acceptable for my application.

    Can you imagine a shorter code to do this?