Hello guys,
I'd been following some other problems on SCI2 based DMA transfers which are answered, but even following the instructions and considering the available solutions, I still could not make my code below to work. The individual byte sent over SCI works fine but DMA does not transmit. I would appreciate anyone who can provide me with some idea how I can make it work and if I am doing something wrong.
Regards
Sohal.
// global for this example
uint8_t datagramToSend[7];
// send data every 200 µs via SCI component of TMS570LS3137
main(){
m_datagramToSend.header = 0xaa;
m_datagramToSend.payload = 0xaaaaaaaa;
m_datagramToSend.crc = 0xaaaa;
sciInit();
dmaInit();
// 5 kHz loop
while(true) {
wait();
dmaSetChEnable(DMA_CH0, DMA_HW);
}
}
/**
* Configure DMA channels for transmission and reception of datagrams.
*/
void SerialPumpPort::dmaInit(){
// TX line, DMA configuration for transmission via SCI bus
dmaReqAssign(DMA_CH0, 31); // assign request line 31 to channel 0
dmaEnableInterrupt(DMA_CH0, BTC); // enable interrupt for block transfer complete
// setting DMA control packets for transmit
g_dmaCTRL dma_control_TX;
dma_control_TX.SADD = (uint32) &datagramToSend; // initial source address
dma_control_TX.CHCTRL = 0; // is overwritten by some of the next commands
dma_control_TX.DADD = (uint32) 0xFFF7E538; // initial destination address
dma_control_TX.FRCNT = 7U; // frame count (ITCOUNT)
dma_control_TX.ELCNT = 1U; // element count (ITCOUNT)
dma_control_TX.ELDOFFSET = 0U; // element destination offset
dma_control_TX.ELSOFFSET = 0U; // element source offset
dma_control_TX.FRDOFFSET = 0U; // frame detination offset
dma_control_TX.FRSOFFSET = 0U; // frame source offset
dma_control_TX.PORTASGN = 4U; // channel 0 assigned to port B (PAR0)
dma_control_TX.RDSIZE = ACCESS_8_BIT; // read element size
dma_control_TX.WRSIZE = ACCESS_8_BIT; // write element size
dma_control_TX.TTYPE = FRAME_TRANSFER; // trigger type - frame/block
dma_control_TX.ADDMODERD = ADDR_INC1; // addresssing mode for source
dma_control_TX.ADDMODEWR = ADDR_FIXED; // addresssing mode for destination
dma_control_TX.AUTOINIT = AUTOINIT_OFF; // auto-init mode
dmaSetCtrlPacket(DMA_CH0, dma_control_TX);
// enable DMA
dmaEnable();
}
/**
* This function initializes the SCI module.
*/
void sciInit(void)
{
/* USER CODE BEGIN (2) */
/* USER CODE END */
/** @b initialize @b SCI */
/** - bring SCI out of reset */
sciREG->GCR0 = 0U;
sciREG->GCR0 = 1U;
/** - Disable all interrupts */
sciREG->CLEARINT = 0xFFFFFFFFU;
sciREG->CLEARINTLVL = 0xFFFFFFFFU;
/** - global control 1 */
sciREG->GCR1 = (uint32)((uint32)1U << 25U) /* enable transmit */
| (uint32)((uint32)1U << 24U) /* enable receive */
| (uint32)((uint32)1U << 5U) /* internal clock (device has no clock pin) */
| (uint32)((uint32)(1U-1U) << 4U) /* number of stop bits */
| (uint32)((uint32)0U << 3U) /* even parity, otherwise odd */
| (uint32)((uint32)0U << 2U) /* enable parity */
| (uint32)((uint32)1U << 1U); /* asynchronous timing mode */
/** - set baudrate */
sciREG->BRS = 3U; /* baudrate */
/** - transmission length */
sciREG->FORMAT = 8U - 1U; /* length */
/** - set SCI pins functional mode */
sciREG->PIO0 = (uint32)((uint32)1U << 2U) /* tx pin */
| (uint32)((uint32)1U << 1U); /* rx pin */
/** - set SCI pins default output value */
sciREG->PIO3 = (uint32)((uint32)0U << 2U) /* tx pin */
| (uint32)((uint32)0U << 1U); /* rx pin */
/** - set SCI pins output direction */
sciREG->PIO1 = (uint32)((uint32)0U << 2U) /* tx pin */
| (uint32)((uint32)0U << 1U); /* rx pin */
/** - set SCI pins open drain enable */
sciREG->PIO6 = (uint32)((uint32)0U << 2U) /* tx pin */
| (uint32)((uint32)0U << 1U); /* rx pin */
/** - set SCI pins pullup/pulldown enable */
sciREG->PIO7 = (uint32)((uint32)0U << 2U) /* tx pin */
| (uint32)((uint32)0U << 1U); /* rx pin */
/** - set SCI pins pullup/pulldown select */
sciREG->PIO8 = (uint32)((uint32)1U << 2U) /* tx pin */
| (uint32)((uint32)1U << 1U); /* rx pin */
/** - set interrupt level */
sciREG->SETINTLVL = (uint32)((uint32)0U << 26U) /* Framing error */
| (uint32)((uint32)0U << 25U) /* Overrun error */
| (uint32)((uint32)0U << 24U) /* Parity error */
| (uint32)((uint32)0U << 9U) /* Receive */
| (uint32)((uint32)0U << 8U) /* Transmit */
| (uint32)((uint32)0U << 1U) /* Wakeup */
| (uint32)((uint32)0U << 0U); /* Break detect */
/** - set interrupt enable */
sciREG->SETINT = (uint32)((uint32)0U << 26U) /* Framing error */
| (uint32)((uint32)0U << 25U) /* Overrun error */
| (uint32)((uint32)0U << 24U) /* Parity error */
| (uint32)((uint32)1U << 9U) /* Receive */
| (uint32)((uint32)0U << 1U) /* Wakeup */
| (uint32)((uint32)0U << 0U); /* Break detect */
// added!!
sciREG->SETINT |= (1 << 18); // set interrupt for RX DMA ALL
sciREG->SETINT |= (1 << 17); // set interrupt for RX DMA
sciREG->SETINT |= (1 << 16); // set interrupt for TX DMA
/** - initialize global transfer variables */
g_sciTransfer_t[0U].mode = (uint32)1U << 8U;
g_sciTransfer_t[0U].tx_length = 0U;
g_sciTransfer_t[0U].rx_length = 0U;
/** - Finaly start SCI */
sciREG->GCR1 |= 0x80U;
}