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TMS570LS0332 digital watchdog

David Sabol
Genius 4850 points
Other Parts Discussed in Thread: HALCOGEN

Hi,

I'm trying to set up the DWD on a TMS570LS0332. 

 

I'm trying to use an rti compare interrupt to service the watchdog, setting the compare period to half of what the timeout value is.

 

The data sheet says the expiration time can be found using

texp = (DWDPRLD + 1) × 2^13/RTICLK

the RTI1CLK is at 80MHz, so I should be able to have a timeout of 0.000102 s up to 0.41943 s

 

I tried using DWDPRLD = 127, which should mean a timeout of 13.1072 ms, so I set CMP[1].UDCPx and CMP[1].COMPx to half of that, 65536.

 

My program flow is

-  initialize the RTI and start the counter

- call dwdInit with my preload value of 127

- call dwdCounterEnable

- enable rti notifications for compare 1

 

When I get the rti notification I service the watchdog by calling dwdReset.

 

My program continually resets because of a windowed watchdog end time violation.  I have tried setting the preload value to 4095 and set the RTI to go off every 1 ms....but I still get the resets because of a timeout condition.

 

Any idea what I am doing wrong?

 

Thanks,

David

  • 0
    TI__Mastermind 22715 points
    David,

    The DWD counter is counting down with RTICLK (80 MHz in your example). The compare unit checks the value in the free running counter. The input to free running counter is RTICLK divided by the upcounter compare register (RTICPUCP0/1). If the upcounter compare register has a value of 9, the free running counter is running at 80/10= 8MHz. Assume that the preload value to the DWD counter is 1000 and you want to compare interrupt to occur when the DWD counter reaches 500. The value in the compare register should be 50.

    Thanks and regards,

    Zhaohong
  • 0 in reply to Zhaohong Zhang
    Genius 4850 points
    Hi,

    I'm still confused.

    The up counter compare register is set to 7, so my actual frequency is 10 MHz.

    But using the numbers you gave, if the upcounter compare register is set to 9 and we have an 8MHz input frequency, if 50 is entered into the rti compare register, that is a period of 6 us. That is pretty fast. The high limit for the preload value for the DWD is 4095, so that would mean the largest timeout period if just over 24 us? I feel like I'm missing something.

    According to the equation given in the TRM, if DWDPRLD is 1000, and RTICLK is 80MHz, the expiration time of the DWD down counter is 0.1025 seconds, so I would want an rti interrupt generated every 50 ms, which according to Halcogen means the compare register should be set to 500000 if the RTICLK is 80MHz and the UC compare is set to 7, giving a counter frequency of 10MHz.

    Thanks,
    David
  • 0 in reply to David Sabol
    TI__Mastermind 22715 points
    David,

    if DWDPRLD is 1000, and RTICLK is 80MHz, the expiration time of the DWD down counter is 0.0125 ms.

    1000/(80x10^6) = 0.0125x10^-3 (second)

    Thanks and regards,

    Zhaohong
  • 0 in reply to Zhaohong Zhang
    Genius 4850 points

    From the TRM for the TMS570LS03x (SPNU517A) section 12.2.4.1

     

     

    Which doesn't match the equation you used, so is the document wrong? Am I using the wrong document?   Dividing the DWDPRLD value by the RTICLK would put the largest expiration time at 0.0512 ms, that seems way too fast for the longest expiration time available.


    David

  • 0 in reply to David Sabol
    TI__Mastermind 22715 points
    David,

    Somehow, I missed it. Sorry for the delay.

    The formula you used is correct. Let's go over the numbers again. Assume a 80MHz RTICLK

    Time to DWD to expire: (127 +1)x8912/80000000 = 0.0143sec (14.3 ms)

    Clock to the RTI free running counter (input to the compare module) = RTICLK/ (RTICPUCx+1). If RTICPUCx = 0, the input to the free running counter is RTICLK/(2^32).

    Assume that RTICPUCx = 1, the input to free running counter is 40 MHz (0.025us period). If UDCPx and COMPx are all set to 65536, the compare interrupt should occur every 0.025x65536= 1638.4 us = 1.684 ms.

    I am guessing that you did not set up the RTICPUCx register for up counter compare. Would you please check for it.

    Hope that this would solve your problem. Sorry again for the delay and confusions.

    Thanks and regards,

    Zhaohong
  • 0 in reply to Zhaohong Zhang
    Genius 4850 points
    Hi,

    I was able to get this working. I'm not sure what the issue was.

    David