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unable to read from memory location Real Timer interrupt (RTI) interrupt

I have code that should be reading the value from RTI->INTFLAG and instead of reading the value that I see in the peripherals menu (I expect 0xF or 0x7) or in the dump window the following lines of code are reading 0x0 after the 4th or 5th function call. 
#define RTI_REG(x)      (*(vuint32 *)(void *)(0xFFFFFC00 + x))
fcBool os_timer_is_done()
{
// don't know why this disagrees with what I see in lauderbach
uint32 timeInt = 0xFFFFFFFF;
        uint32 timeInt2 = 0xFFFFFFFF;
fcBool returnVal = FALSE;
timeInt = RTI->INTFLAG;
        timeInt2 = RTI_REG(0x88);
if(  ((timeInt & 0x4) == 0x4) || ((timeInt2 & 0x4) == 0x4))
{
timer_stop(RTI, 1); // stop timer in global control register
returnVal = TRUE;
}
return returnVal;
}
setup:
free running counter starts at 0
clear interrupt flag
set compare up counter register to 1
set compare register to the end value
set update compare register to the same value as compare register
disable auto clear in the compare interrupt clear enable register
start timer in global compare register
I also tried enabling the timer interrupt, but same result
  • Hi Laura,

    Is it possible for you to provide either the entire project or a simplified project with just this task so we can have a look at it. Unfortunately, I can't determine what might be going on with just the information provided above.
  • when I set a break point to check the value of timeInt and timeInt2 they are reading 0 from RTI interrupt register.  When I dump this memory location, the value is not zero. Why?

    #define RTI_REG(x) (*(vuint32 *)(void *)(0xFFFFFC00 + x))


    // **************************************************************************
    // Function: timer_start
    // Iteration Rate: On Demand
    // Description: Starts the RTI timer on the given channel.
    // Constraints: None
    // ***************************************************************************
    void timer_start(rtiBASE_t *rtiREG, uint32 counter)
    {
    rtiREG->GCTRL |= (1U << (counter & 3U));
    }

    // **************************************************************************
    // Function: timer_stop
    // Iteration Rate: On Demand
    // Description: Stops the RTI timer on the given channel.
    // Constraints: None
    // ***************************************************************************
    void timer_stop(rtiBASE_t *rtiREG, uint32 counter)
    {
    rtiREG->GCTRL &= ~(1U << (counter & 3U));
    }


    // **************************************************************************
    // Function: timer_reset
    // Iteration Rate: On Demand
    // Description: Resets the RTI timer on the given channel.
    // Constraints: None
    // ***************************************************************************
    uint32 timer_reset(rtiBASE_t *rtiREG, uint32 counter)
    {
    uint32 success = 0U;
    uint8 i;

    if ((!(rtiREG->GCTRL & (1U << (counter & 3U)))) != 0U)
    {
    rtiREG->CNT[counter].UCx = 0x00000000U;
    rtiREG->CNT[counter].FRCx = 0x00000000U;

    /* Reset all the compare registers associated with this counter */
    for (i = 0; i < 4; i++)
    {
    if (((rtiREG->COMPCTRL >> (i*4)) & 0x00000001) == counter)
    {
    rtiREG->CMP[i].COMPx = 0;
    }
    }

    success = 1U;
    }

    return success;
    }


    // *****************************************************************************
    // Function: os_timer_setup
    // Iteration Rate: On demand
    // Description: RTI 2 is used as a delay (polling) timer. it is
    // loaded with startVal and sets the timer interrupt flag when it has
    // reached zero
    // param: startVal is a value in nano-seconds
    // *****************************************************************************
    void os_timer_setup(uint32 startVal)
    {

    /** - Setup input source compare 0-3 */
    /* COMP3 & 2 - FRC1 (50MHz)
    * COMP1 & 0 - FRC0 (100KHz) */
    RTI->COMPCTRL = 0x00001000U | 0x00000100U | 0x00000000U | 0x00000000U;

    /** - Disable counter block 1 */
    timer_stop(RTI, 1);

    /** - Reset up counter 1 */
    timer_reset(RTI, 1);

    // clear interrupt to reset the counter
    RTI->INTFLAG |= 0x4;

    /** - Setup up counter 1 compare value
    * - 0x00000000: Divide by 2^32
    * - 0x00000001-0xFFFFFFFF: Divide by (CPUC1 + 1)
    */
    RTI->CNT[1U].CPUCx = ((RTI_MHz * 1000000)/RTI_1_FRC_HZ) - 1U;

    /** - Setup compare 2 value. This value is compared with selected free running counter. */
    RTI->CMP[2U].COMPx = startVal / 20;

    /** - Setup update compare 2 value. This value is added to the compare 2 value on each compare match. */
    RTI->CMP[2U].UDCPx = 0;

    /* No auto-clear on channel 1 */
    RTI->INTCLRENABLE &= 0xFF00FFFF;
    RTI->INTCLRENABLE |= 0x00050000;

    /** - Enable counter block 1 */
    timer_start(RTI, 1);

    }

    // *****************************************************************************
    // Function: os_timer_is_done
    // Iteration Rate: On demand
    // Description: returns TRUE when timer has counted down to zero
    // Constraints: None
    // *****************************************************************************
    fcBool os_timer_is_done()
    {
    // don't know why this disagrees with what I see in lauderbach
    uint32 timeInt = 0xFFFFFFFF;
    uint32 timeInt2 = 0xFFFFFFFF;
    // when update comp is zero then the comp is not updated when the time expires
    uint32 timeCapture = RTI->CNT[1U].FRCx;
    uint32 timeCompare = RTI->CMP[2U].COMPx;
    uint32 returnVal = 0;
    timeInt = RTI->INTFLAG;
    timeInt2 = RTI_REG(0x88);

    if( (timeCapture > timeCompare) || ((timeInt & 0x4) == 0x4) )
    {
    timer_stop(RTI, 1);
    returnVal = 1U;
    }

    return returnVal;
    }

  • Hi Laura,

    I am not able to use the code listings provided to see what might be the issue. Do you have a CCS project that you can zip and post so that I have the same clock settings and function calls that you have? This will allow me to step through the code to see if I can recreate your issue and try to work out a solution or an explanation of that is happening.