Hercules Rm48L952ZWT Repurposed M17- EMIF_nCS[4]/RTP_DATA[7] as GPIO

Tammy Noergaard

Other Parts Discussed in Thread: HALCOGEN

Hi. We are using the Hercules RM48L952ZWT board. If we set in HalCoGen, that we want to use Terminal M17 M17- EMIF_nCS[4]/RTP_DATA[7] as GPIO. Under the HalCoGen RTP tab, we can see where to set RTP_DATA[7] to a GPIO.

1. In PINMUX M17 terminal tab, do we want to select the RTP_DATA[7] so it is used as GPIO as we configured in RTP, or do we not select anything for it to work as a GPIO.

2. In the software how can we get to this pin to change it's settings to 0 or 1? Is there an initialization function that needs to be run so the HalCoGen settings as this terminal M17 us being GPIO is executed at poweron and it is the default as we configured in HalCoGen?

Thank you

over 9 years ago

0 Chuck Davenport over 9 years ago

TI__Guru 59540 points

Hi Tammy,

To use RTP_DATA[7] (terminal M17) as GPIO, you would configure the pin mux tab to select the RTP_DATA[7] function on this terminal as shown here:

You would also need to configure the pin in the RTP tab as shown below:

In this view, you can select the RTP_DATA[7] signal to be a GPIO, the I/O direction, open drain or not, the pull direction/enable/disable, and the initial signal level if an output.

To control the output/read the input on this pin, there are registers that you could be used as noted in the TRM (RTPPCx). However, the recommended use is to utilize the #defined rtpPORT in reg_rtp.h in conjunction with the GIO drivers in gio.c to set/clear/read the pin levels.

0 Tammy Noergaard over 9 years ago in reply to Chuck Davenport

Genius 3665 points

Hi Thank you. We did this thank you. But when booting up the board it did not seem to have an effect. Was there a function call we needed to make to be sure that the initialization of this based on HalCoGen was executed?

It only worked after we manually changed the registers in the software to reflect what you showed us to do above i.e.,

/* RTP set all pins to functional */

rtpREG->PC0 = (uint32) 0U /* DATA[0] */

| (uint32)((uint32)0U << 1U) /* DATA[1] */

| (uint32)((uint32)0U << 2U) /* DATA[2] */

| (uint32)((uint32)0U << 3U) /* DATA[3] */

| (uint32)((uint32)0U << 4U) /* DATA[4] */

| (uint32)((uint32)0U << 5U) /* DATA[5] */

| (uint32)((uint32)0U << 6U) /* DATA[6] */

| (uint32)((uint32)0U << 7U) /* DATA[7] */

| (uint32)((uint32)0U << 8U) /* DATA[8] */

| (uint32)((uint32)0U << 9U) /* DATA[9] */

| (uint32)((uint32)0U << 10U) /* DATA[10] */

| (uint32)((uint32)0U << 11U) /* DATA[11] */

| (uint32)((uint32)0U << 12U) /* DATA[12] */

| (uint32)((uint32)0U << 13U) /* DATA[13] */

| (uint32)((uint32)0U << 14U) /* DATA[14] */

| (uint32)((uint32)0U << 15U) /* DATA[15] */

| (uint32)((uint32)0U << 16U) /* RTP SYNC */

| (uint32)((uint32)0U << 17U) /* RTP CLK */

| (uint32)((uint32)0U << 18U); /* RTP ENA */

/** - RTP Port direction */

rtpREG->PC1 = (uint32) 1U /* DATA[0] */

| (uint32)((uint32)1U << 1U) /* DATA[1] */

| (uint32)((uint32)1U << 2U) /* DATA[2] */

| (uint32)((uint32)1U << 3U) /* DATA[3] */

| (uint32)((uint32)1U << 4U) /* DATA[4] */

| (uint32)((uint32)1U << 5U) /* DATA[5] */

| (uint32)((uint32)1U << 6U) /* DATA[6] */

| (uint32)((uint32)1U << 7U) /* DATA[7] */

| (uint32)((uint32)1U << 8U) /* DATA[8] */

| (uint32)((uint32)1U << 9U) /* DATA[9] */

| (uint32)((uint32)1U << 10U) /* DATA[10] */

| (uint32)((uint32)1U << 11U) /* DATA[11] */

| (uint32)((uint32)1U << 12U) /* DATA[12] */

| (uint32)((uint32)1U << 13U) /* DATA[13] */

| (uint32)((uint32)1U << 14U) /* DATA[14] */

| (uint32)((uint32)1U << 15U) /* DATA[15] */

| (uint32)((uint32)1U << 16U) /* RTP SYNC */

| (uint32)((uint32)1U << 17U) /* RTP CLK */

| (uint32)((uint32)1U << 18U); /* RTP ENA */

/** - RTP Port open drain enable */

rtpREG->PC6 = (uint32) 1U /* DATA[0] */

| (uint32)((uint32)1U << 1U) /* DATA[1] */

| (uint32)((uint32)1U << 2U) /* DATA[2] */

| (uint32)((uint32)1U << 3U) /* DATA[3] */

| (uint32)((uint32)1U << 4U) /* DATA[4] */

| (uint32)((uint32)1U << 5U) /* DATA[5] */

| (uint32)((uint32)1U << 6U) /* DATA[6] */

| (uint32)((uint32)1U << 7U) /* DATA[7] */

| (uint32)((uint32)1U << 8U) /* DATA[8] */

| (uint32)((uint32)1U << 9U) /* DATA[9] */

| (uint32)((uint32)1U << 10U) /* DATA[10] */

| (uint32)((uint32)1U << 11U) /* DATA[11] */

| (uint32)((uint32)1U << 12U) /* DATA[12] */

| (uint32)((uint32)1U << 13U) /* DATA[13] */

| (uint32)((uint32)1U << 14U) /* DATA[14] */

| (uint32)((uint32)1U << 15U) /* DATA[15] */

| (uint32)((uint32)1U << 16U) /* RTP SYNC */

| (uint32)((uint32)1U << 17U) /* RTP CLK */

| (uint32)((uint32)1U << 18U); /* RTP ENA */

/** - RTP Port pullup / pulldown enable*/

rtpREG->PC7 = (uint32) 0U /* DATA[0] */

| (uint32)((uint32)0U << 1U) /* DATA[1] */

| (uint32)((uint32)0U << 2U) /* DATA[2] */

| (uint32)((uint32)0U << 3U) /* DATA[3] */

| (uint32)((uint32)0U << 4U) /* DATA[4] */

| (uint32)((uint32)0U << 5U) /* DATA[5] */

| (uint32)((uint32)0U << 6U) /* DATA[6] */

| (uint32)((uint32)0U << 7U) /* DATA[7] */

| (uint32)((uint32)0U << 8U) /* DATA[8] */

| (uint32)((uint32)0U << 9U) /* DATA[9] */

| (uint32)((uint32)0U << 10U) /* DATA[10] */

| (uint32)((uint32)0U << 11U) /* DATA[11] */

| (uint32)((uint32)0U << 12U) /* DATA[12] */

| (uint32)((uint32)0U << 13U) /* DATA[13] */

| (uint32)((uint32)0U << 14U) /* DATA[14] */

| (uint32)((uint32)0U << 15U) /* DATA[15] */

| (uint32)((uint32)0U << 16U) /* RTP SYNC */

| (uint32)((uint32)0U << 17U) /* RTP CLK */

| (uint32)((uint32)0U << 18U); /* RTP ENA */

/** - RTP Port pullup / pulldown selection */

rtpREG->PC8 = (uint32) 1U /* DATA[0] */

| (uint32)((uint32)1U << 1U) /* DATA[1] */

| (uint32)((uint32)1U << 2U) /* DATA[2] */

| (uint32)((uint32)1U << 3U) /* DATA[3] */

| (uint32)((uint32)1U << 4U) /* DATA[4] */

| (uint32)((uint32)1U << 5U) /* DATA[5] */

| (uint32)((uint32)1U << 6U) /* DATA[6] */

| (uint32)((uint32)1U << 7U) /* DATA[7] */

| (uint32)((uint32)1U << 8U) /* DATA[8] */

| (uint32)((uint32)1U << 9U) /* DATA[9] */

| (uint32)((uint32)1U << 10U) /* DATA[10] */

| (uint32)((uint32)1U << 11U) /* DATA[11] */

| (uint32)((uint32)1U << 12U) /* DATA[12] */

| (uint32)((uint32)1U << 13U) /* DATA[13] */

| (uint32)((uint32)1U << 14U) /* DATA[14] */

| (uint32)((uint32)1U << 15U) /* DATA[15] */

| (uint32)((uint32)1U << 16U) /* RTP SYNC */

| (uint32)((uint32)1U << 17U) /* RTP CLK */

| (uint32)((uint32)1U << 18U); /* RTP ENA */

/** - RTP Port output values */

rtpREG->PC3 = (uint32) 0U /* DATA[0] */

| (uint32)((uint32)0U << 1U) /* DATA[1] */

| (uint32)((uint32)0U << 2U) /* DATA[2] */

| (uint32)((uint32)0U << 3U) /* DATA[3] */

| (uint32)((uint32)0U << 4U) /* DATA[4] */

| (uint32)((uint32)0U << 5U) /* DATA[5] */

| (uint32)((uint32)0U << 6U) /* DATA[6] */

| (uint32)((uint32)0U << 7U) /* DATA[7] */

| (uint32)((uint32)0U << 8U) /* DATA[8] */

| (uint32)((uint32)0U << 9U) /* DATA[9] */

| (uint32)((uint32)0U << 10U) /* DATA[10] */

| (uint32)((uint32)0U << 11U) /* DATA[11] */

| (uint32)((uint32)0U << 12U) /* DATA[12] */

| (uint32)((uint32)0U << 13U) /* DATA[13] */

| (uint32)((uint32)0U << 14U) /* DATA[14] */

| (uint32)((uint32)0U << 15U) /* DATA[15] */

| (uint32)((uint32)0U << 16U) /* RTP SYNC */

| (uint32)((uint32)0U << 17U) /* RTP CLK */

| (uint32)((uint32)0U << 18U); /* RTP ENA */

0 Chuck Davenport over 9 years ago in reply to Tammy Noergaard

TI__Guru 59540 points

Hi Tammy,

You would need to call muxInit() from the pinmux.c file and rtpInit() from the rtp.c files. The calls to these would most likely go in you main or possible in a user code section of sys_startup.c if you want the changes to be in effect as quickly as possible.

The code you show above is the code from rtpInit(); correct? Below is the same code from my project where I only modified the rtp_data[7] pin to be a GPIO output configured with initial value of 1, pull up enabled,

void rtpInit(void)
{

/* USER CODE BEGIN (2) */
/* USER CODE END */

/** @b intalise @b RTP */

/** @b initialize @b RTP @b Port */

/** - RTP Port output values */
rtpREG->PC3 = (uint32) 0U /* DATA[0] */
| (uint32)((uint32)0U << 1U) /* DATA[1] */
| (uint32)((uint32)0U << 2U) /* DATA[2] */
| (uint32)((uint32)0U << 3U) /* DATA[3] */
| (uint32)((uint32)0U << 4U) /* DATA[4] */
| (uint32)((uint32)0U << 5U) /* DATA[5] */
| (uint32)((uint32)0U << 6U) /* DATA[6] */
| (uint32)((uint32)1U << 7U) /* DATA[7] */<--- OUTPUT 1
| (uint32)((uint32)0U << 8U) /* DATA[8] */
| (uint32)((uint32)0U << 9U) /* DATA[9] */
| (uint32)((uint32)0U << 10U) /* DATA[10] */
| (uint32)((uint32)0U << 11U) /* DATA[11] */
| (uint32)((uint32)0U << 12U) /* DATA[12] */
| (uint32)((uint32)0U << 13U) /* DATA[13] */
| (uint32)((uint32)0U << 14U) /* DATA[14] */
| (uint32)((uint32)0U << 15U) /* DATA[15] */
| (uint32)((uint32)0U << 16U) /* RTP SYNC */
| (uint32)((uint32)0U << 17U) /* RTP CLK */
| (uint32)((uint32)0U << 18U); /* RTP ENA */

/** - RTP Port direction */
rtpREG->PC1 = (uint32) 1U /* DATA[0] */
| (uint32)((uint32)1U << 1U) /* DATA[1] */
| (uint32)((uint32)1U << 2U) /* DATA[2] */
| (uint32)((uint32)1U << 3U) /* DATA[3] */
| (uint32)((uint32)0U << 4U) /* DATA[4] */
| (uint32)((uint32)1U << 5U) /* DATA[5] */
| (uint32)((uint32)1U << 6U) /* DATA[6] */
| (uint32)((uint32)1U << 7U) /* DATA[7] */<--DIR = Output
| (uint32)((uint32)0U << 8U) /* DATA[8] */
| (uint32)((uint32)1U << 9U) /* DATA[9] */
| (uint32)((uint32)1U << 10U) /* DATA[10] */
| (uint32)((uint32)0U << 11U) /* DATA[11] */
| (uint32)((uint32)0U << 12U) /* DATA[12] */
| (uint32)((uint32)1U << 13U) /* DATA[13] */
| (uint32)((uint32)1U << 14U) /* DATA[14] */
| (uint32)((uint32)0U << 15U) /* DATA[15] */
| (uint32)((uint32)0U << 16U) /* RTP SYNC */
| (uint32)((uint32)1U << 17U) /* RTP CLK */
| (uint32)((uint32)1U << 18U); /* RTP ENA */

/** - RTP Port open drain enable */
rtpREG->PC6 = (uint32) 0U /* DATA[0] */
| (uint32)((uint32)0U << 1U) /* DATA[1] */
| (uint32)((uint32)0U << 2U) /* DATA[2] */
| (uint32)((uint32)0U << 3U) /* DATA[3] */
| (uint32)((uint32)0U << 4U) /* DATA[4] */
| (uint32)((uint32)0U << 5U) /* DATA[5] */
| (uint32)((uint32)0U << 6U) /* DATA[6] */
| (uint32)((uint32)0U << 7U) /* DATA[7] */<--OD = disabled
| (uint32)((uint32)0U << 8U) /* DATA[8] */
| (uint32)((uint32)0U << 9U) /* DATA[9] */
| (uint32)((uint32)0U << 10U) /* DATA[10] */
| (uint32)((uint32)0U << 11U) /* DATA[11] */
| (uint32)((uint32)0U << 12U) /* DATA[12] */
| (uint32)((uint32)0U << 13U) /* DATA[13] */
| (uint32)((uint32)0U << 14U) /* DATA[14] */
| (uint32)((uint32)0U << 15U) /* DATA[15] */
| (uint32)((uint32)0U << 16U) /* RTP SYNC */
| (uint32)((uint32)0U << 17U) /* RTP CLK */
| (uint32)((uint32)0U << 18U); /* RTP ENA */

/** - RTP Port pullup / pulldown selection */
rtpREG->PC8 = (uint32) 1U /* DATA[0] */
| (uint32)((uint32)1U << 1U) /* DATA[1] */
| (uint32)((uint32)1U << 2U) /* DATA[2] */
| (uint32)((uint32)1U << 3U) /* DATA[3] */
| (uint32)((uint32)1U << 4U) /* DATA[4] */
| (uint32)((uint32)1U << 5U) /* DATA[5] */
| (uint32)((uint32)1U << 6U) /* DATA[6] */
| (uint32)((uint32)1U << 7U) /* DATA[7] */<--PU selected
| (uint32)((uint32)1U << 8U) /* DATA[8] */
| (uint32)((uint32)1U << 9U) /* DATA[9] */
| (uint32)((uint32)1U << 10U) /* DATA[10] */
| (uint32)((uint32)1U << 11U) /* DATA[11] */
| (uint32)((uint32)1U << 12U) /* DATA[12] */
| (uint32)((uint32)1U << 13U) /* DATA[13] */
| (uint32)((uint32)1U << 14U) /* DATA[14] */
| (uint32)((uint32)1U << 15U) /* DATA[15] */
| (uint32)((uint32)1U << 16U) /* RTP SYNC */
| (uint32)((uint32)1U << 17U) /* RTP CLK */
| (uint32)((uint32)1U << 18U); /* RTP ENA */

/** - RTP Port pullup / pulldown enable*/
rtpREG->PC7 = (uint32) 0U /* DATA[0] */
| (uint32)((uint32)0U << 1U) /* DATA[1] */
| (uint32)((uint32)0U << 2U) /* DATA[2] */
| (uint32)((uint32)0U << 3U) /* DATA[3] */
| (uint32)((uint32)0U << 4U) /* DATA[4] */
| (uint32)((uint32)0U << 5U) /* DATA[5] */
| (uint32)((uint32)0U << 6U) /* DATA[6] */
| (uint32)((uint32)0U << 7U) /* DATA[7] */<--Pull enabled
| (uint32)((uint32)0U << 8U) /* DATA[8] */
| (uint32)((uint32)0U << 9U) /* DATA[9] */
| (uint32)((uint32)0U << 10U) /* DATA[10] */
| (uint32)((uint32)0U << 11U) /* DATA[11] */
| (uint32)((uint32)0U << 12U) /* DATA[12] */
| (uint32)((uint32)0U << 13U) /* DATA[13] */
| (uint32)((uint32)0U << 14U) /* DATA[14] */
| (uint32)((uint32)0U << 15U) /* DATA[15] */
| (uint32)((uint32)0U << 16U) /* RTP SYNC */
| (uint32)((uint32)0U << 17U) /* RTP CLK */
| (uint32)((uint32)0U << 18U); /* RTP ENA */

/* RTP set all pins to functional */
rtpREG->PC0 = (uint32) 1U /* DATA[0] */
| (uint32)((uint32)1U << 1U) /* DATA[1] */
| (uint32)((uint32)1U << 2U) /* DATA[2] */
| (uint32)((uint32)1U << 3U) /* DATA[3] */
| (uint32)((uint32)1U << 4U) /* DATA[4] */
| (uint32)((uint32)1U << 5U) /* DATA[5] */
| (uint32)((uint32)1U << 6U) /* DATA[6] */
| (uint32)((uint32)0U << 7U) /* DATA[7] */<--Pin in GPIO mode / Functional mode disabled
| (uint32)((uint32)1U << 8U) /* DATA[8] */
| (uint32)((uint32)1U << 9U) /* DATA[9] */
| (uint32)((uint32)1U << 10U) /* DATA[10] */
| (uint32)((uint32)1U << 11U) /* DATA[11] */
| (uint32)((uint32)1U << 12U) /* DATA[12] */
| (uint32)((uint32)1U << 13U) /* DATA[13] */
| (uint32)((uint32)1U << 14U) /* DATA[14] */
| (uint32)((uint32)1U << 15U) /* DATA[15] */
| (uint32)((uint32)1U << 16U) /* RTP SYNC */
| (uint32)((uint32)1U << 17U) /* RTP CLK */
| (uint32)((uint32)1U << 18U); /* RTP ENA */

/* USER CODE BEGIN (3) */
/* USER CODE END */

}

0 Tammy Noergaard over 9 years ago in reply to Chuck Davenport

Genius 3665 points

Hi Chuck. Thank you. Is there a certain order things should be initialized in our boot up code i.e.,
muxInit(); /* initialize muliplexing configuration */

/* Initialize memory protection unit.
* Region configurations are selected using MPU Tab in HALCoGen.
* MPU is enabled in mpuInit function if "Enable MPU" in GUI is selected */
_mpuInit_();

hetInit(); /* initialize NHET */
adcInit(); /* initialize adc */
gioInit(); /* initialize gpio */
esmInit(); /* Configure ESM module to capture esm errors on Error Pin*/
i2cInit(); /* i2c initialization */
mibspiInit(); /* initializing mibspi */
....

or does it not matter the order? Thank you again.

0 Chuck Davenport over 9 years ago in reply to Tammy Noergaard

TI__Guru 59540 points

Hi Tammy,

There is an application note that describes the recommended sequences of most of what you are talking about. It is spns106d which is located at this link:
www.ti.com/.../litabsmultiplefilelist.tsp;tabId=1502&literatureNumber=spna106d&docCategoryId=1&familyId=2056&keyMatch=spna106d&tisearch=Search-EN-Everything

I think this should help with your question. Aside from the recommendations in this document, I think it is really a matter of your system/application requirements.

0 Chuck Davenport over 9 years ago in reply to Chuck Davenport

TI__Guru 59540 points

The link did not come through very well on my prior post. Here is the link again for the startup sequence app note:

www.ti.com/.../spna106

0 Tammy Noergaard over 9 years ago in reply to Chuck Davenport

Genius 3665 points

Hi Thank you. You are correct, it is based on the rtpInit. When we regenerated using 4.03.00 HalCoGen with these changes, the rtpInit function did not reflect what we did (i.e., what you showed screen shots of) but the autogenerated code was different. That is why we we did it manually like I copied and pasted for you. Was there more that needed to be done so that HalCoGen autogenerated the code for these registers to be initialized the way we set it in the HalCoGen GUI? Or is this a known issue, and we just set these registers manually in GIO mode? Thank you again.

0 Chuck Davenport over 9 years ago in reply to Tammy Noergaard

TI__Guru 59540 points

Hi Tammy,

I forwarded your post to our Halcogen team lead so he could review it. As you observed from my post, I was able to generate the code from Halcogen 4.03.00 so I am not sure what might have caused the glitch where the code wasn't generated correctly. One thing to try is to make sure the configurations on the RTP tab is saved within the project. i.e., what happens when you exit and re-enter the application and are your changes; somehow, not registering in the application. Before you generate the code, make sure you have saved the project is another thing to try.

0 Tammy Noergaard over 9 years ago in reply to Chuck Davenport

Genius 3665 points

Hi Thank you. I did as you suggested and now it is Ok. Can we also repurpose Terminal L17 EMIF_nCS[2] as GIO (output is what we wante dto do). We are only using EMIF_nCS[0] . But when I looked into HalCoGen, I could not see an option for setting L17 EMIF_nCS[2] as GIO output port. If we can, how can we control it like RTP repurposed as GIO (output) above? Thank you again.

0 Veena Kamath over 9 years ago in reply to Tammy Noergaard

TI__Mastermind 31525 points

Hi Tammy,

The pin EMIF_nCS[2] (terminal L17) is not muxed with any of the other pins. That is the reason why it is not present in the HALCoGen Pinmux Tab.

The EMIF module does not provide a feature to configure its pins as GIO.

Thanks and Regards,

Veena

Arm-based microcontrollers

Arm-based microcontrollers forum

Hercules Rm48L952ZWT Repurposed M17- EMIF_nCS[4]/RTP_DATA[7] as GPIO