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Cache Maintenance Query

lyf sci
Genius 3720 points

Hi Experts,

In the Hercules Micro controllers using the Cortex R4 how the cache coherency is maintained ?

Like when the external memory regions are configured as cache  and when DMA needs to be invoked from the external memory does the software needs to maintain the cache coherency or DMA will internally take care of it ?

  • 0
    TI__Mastermind 23000 points
    Hello,
    In most MCUs, there is no hardware support for cache coherency. Coherency must be managed by software semaphores and manual cache maintenance operations between CPUs. For non-CPU bus masters, care must be taken to use a combination of CPU software, separate data buffers, and interrupts to ensure cache coherency. The Cortex R4 fits into this category of MCU core and this is one reason why Hercules does not use the R4 in a cached configuration.

    The R5 has limited cache coherency support in hardware, which is one reason TI uses it over the R4 in the cached Hercules products. The Cortex R5 has hardware support for what ARM calls I/O cache coherency. In this scheme the ACP, or accelerator coherency port, is used by the non-CPU bus masters to access the L2 memory. On writes, a small logic called the "snoop control unit" or SCU delays the write response signal back to the bus master until it checks to see if the address written is currently in one of the CPU caches. If the written address is already cached, the line is set as invalid in the cache, which will force the CPU to refetch the line and read the updated data. CPU to CPU cache coherency operations are still done by software in this scheme. You can find more details on this feature in the Cortex R5 Technical Reference Manual from ARM.

    Regards,
    Karl
  • 0 in reply to KGreb
    TI__Mastermind 22715 points
    As Karl explained, the cache coherency for the on-chip L2 memory is automatically handled by the ACP module. However, the user still need to handle the cache coherency for external memories by software.

    Thanks and regards,

    Zhaohong