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Trouble accessing SDRAM on RM48 HDK

Anila Soomro
Intellectual 570 points
Other Parts Discussed in Thread: HALCOGEN

Hi,

I am using RM48 HDK and trying to access the on-board 8MB ISSI SDRAM.

The HalCoGen version I am using is 03.02.02. I created a TMDXRM48HDK project, and enabled EMIF and configured the SDRAM settings (according to the values mentioned in its datasheet).

I also configured the EMIF clock (VCLK3) to 53.333 MHz (as this was mentioned in one of the discussions on this forum).

I also changed the linker file manually and defined a section for SDRAM.

After doing the above configurations, I call EMIF_Init function and then write in SDRAM. I am not getting the expected output. First, every operation (16-bit) is updating the entire memory, this I view in the memory viewer (0x8000_0000 and onwards). Secondly, first two write operations are filling the SDRAM with all 0s, and then alternately the correct value is written but on all locations of SDRAM.

What can I do to fix this, what is it that is missed in the entire configuration?

Kindly help.

Thanks

dranne

  • 0
    TI__Guru**** 186226 points

    5127.TMS570 HDK SDRAM Test.zipHi Dranne,

    Attached please find my CCS project for accessing SDRAM on TMS570LS31x HDK. Please change the device name and the runtime support library for your device. 

    Regards,

    QJ

  • 0 in reply to QJ Wang
    Intellectual 570 points
    Thanks very much, I'll surely try this and post the results.

    However, I would like to tell you what else I tried. I updated the HalCoGen to the latest version 04.04.00 and then recreated the project for TMDXRM48HDK, changed the VCLK3 frequency to 66.666 MHz and then called emif_SDRAMInit() but everything seemed to stop working, there are no exceptions but even the bad initialization of SDRAM didn't occur. All the memory just remains 0 all the times.

    Is there some initialization function that needs to be called prior to emif_SDRAMInit()?

    Regards
    dranne
  • 0 in reply to Anila Soomro
    TI__Guru**** 186226 points
    Hi dranne,

    Please try the maximum values for SDRAM timing parameters, and change the refresh rate for new SDRAM frequency.
    refresh_rate = sdram_freq*64000/4096;

    Regards,
    QJ
  • 0 in reply to QJ Wang
    Intellectual 570 points
    Hi,

    I have tried to study your code for configuring SDRAM, I think you have used other procedure than what HalCoGen generates for initializing SDRAM. As such I haven't been able to use your function.

    Secondly my observation is this, the new version of HalCoGen keeps the refresh rate at 31 (last line of emif_SDRAMInit( ) function) no matter what frequency you set (which in my opinion is not correct, may be its a problem with HalCoGen or am I not using it correctly).

    I would request TI to share working code for accessing the on-board SDRAM on RM48HDK, till now whatever I have tried doesn't seem to work. If you say I can send you my CCS and HalCoGen projects, (both new and old versions).

    (PS: I tried changing the refresh rate with new frequency of EMIF, it didn't work)

    Any help would be appreciated.

    Regards
    dranne
  • 0 in reply to Anila Soomro
    Intellectual 570 points
    Hi QJWang:

    Thanks for your help so far.
    I have a good news. Everything started working once I checked the "Gate OFF EMIF_CLK output" in the special muxing option. I had not checked it before because I think I read somewhere on the forum to keep it unchecked.

    Can you please tell me what is the purpose of this special muxing option?

    Thanks & Regards
    dranne
  • 0 in reply to Anila Soomro
    TI__Guru 65580 points
    Yes the name is wrong in HalCoGen - you check the box to enable the EMIF_CLK.
    The EMIF_CLK is disabled by default for EMC reasons and since many applications may not use the EMIF.