TMS570LS31x PCR PSPwrDwn Register Documentation Mismatch

Alex,

Each peripheral select (PS) addresses a 1KB region. This region is then divided into four quadrants [3 - 0], with each quadrant being 256 bytes. These quadrants are then assigned to individual peripheral module control/status registers, as specified in the datasheet SPNS162.

Some peripheral register frames fit within a quadrant, while some other peripherals take two quadrants. The FlexRay controller takes two complete peripheral selects, so that it uses eight quadrants.

The PSPWRDWNSETx/CLRx register bits for the peripherals are assigned as shown in the below chart:

The bits to enable/disable clocks to peripherals that fit within a quadrant are easy to identify. Peripherals that take two quadrants are either controlled by bits that affect quadrant 0 or quadrant 2, as shown in the chart.

Consider the example of MibSPI1 and SPI2 registers:

MibSPI1 registers are in the two quadrants of PS2 from 0xfff7_f400 to 0xfff7_f5ff.

And SPI2 registers are in the two quadrants of PS2 from 0xfff7_f600 to 0xfff7_f7ff.

The controls for the four quadrants of PS2 are in the register PSPWRDWNSET0/CLR0 register bits 11 to 8. Going by the above chart, the clocks to MibSPI1 are controlled by bit 8 and the clocks to SPI2 are controlled by bit 10.

Bits 9 and 11 are unused, and will read as zeros.

Hope this helps. This information does belong in the TRM, and we will try to include it in the next go around.

Regards,

Sunil

Hi Alex,

Sorry for losing track of these questions. Answers below:

1. You refer to SPNS162 for the information on Quadrants and PSPDWNSET/CLR registers, but this dociument does not contain any of those words (quadrand or PSPDWN). The only hint of a reference for this subject is in Table 4-21 Device Memory Map, but quadrant allocation is not mentioned.

>> SPNS162 does specify the actual peripheral select (PS) number to which a certain peripheral is assigned. You are right in that the actual quadrant or quadrants assignment is not specified.

2. The Table 2-1 that you present contradicts itself. What document is this table from? On the first line, for example, number of assigned quadrants is 1, but all for quadrants are checked on this line. How am I suppose to understand this?

>> This figure shows that for a peripheral of a register frame size smaller than or equal to 256 bytes, just one quadrant of the peripheral select is required. Then each quadrant of that peripheral select could be used to address a separate peripheral.

3. You are saying that MibSPI1 and SPI2 have 2 quadrants each. Per Figure 1 in SPNA173, PSPWRDWNSET/CLR registers each quadrant is one bit, so why wouldn't MibSPI1 be allocated to bits 8 and 9 and SPI2 to bits 10 and 11? This is the main thing that I don't understand.

>> When a peripheral occupies more than one quadrant of the PS memory, then only the lower-order control bit (bit 8 or bit 10 in your example) is used to address that peripheral. This is also what is indicated by the figure I posted in my earlier post (row # 2 in the table for 256 bytes < peripheral size < 512 bytes).

Regards,
Sunil