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HALCoGen TMS570LC43x Help confusion: example_mibspi_loopback

Jan Cumps
Guru 15740 points
Other Parts Discussed in Thread: HALCOGEN

In the HALCoGen 04.05.00 help file for the TMS570LC43x, there's an example for mibspi_loopback.

I'm confused with these instructions:

Step 3:

Enable Interrupts

  • Enable all MIBSPI interrupts in the MIBSPI VIM Channels tab.

What TABS/Interrupts are we talking about?

All (High and Low) Interrupts for MIBSPIx on VIM CHANNEL 0 --> 63?

The interrupts on the MIPSPIx Global TABS?

Or another combination?

  • 0
    Guru 15740 points

    (additional remark: the comments in the source for that example refer to CAN a few times - it may be worth changing that to MIBSPI for a next release)

    This one appears in the source file in Hercules\HALCoGen\v04.05.00\examples\TMS570LC43x\example_mibspi_loopback.c only, not in the help file:

     /** - configuring CAN1 MB1,Msg ID-1 to transmit and CAN2 MB1 to receive */

    This one appears both in the source file in Hercules\HALCoGen\v04.05.00\examples\TMS570LC43x\example_mibspi_loopback.c only, and in the help file:

    /* can interrupt notification */

  • 0 in reply to Jan Cumps
    TI__Guru 65580 points

    Hi Jan,

    Thanks for the feedback -- I'm guessing you probably know the answer and are trying to help us improve the docs but just in case,  it should be the MibSPI1 - MibSPI5 High Level interrupts,

    assuming that all the MibSPI interrupts are configured as shown in the picture below from the docs.  (although it only shows MibSPI1 here, the code seems to be using all 5 MibSPIs. )

    Actually IMO the distinction between low and high level interrupt requests from the MibSPI probably isn't shown off well by this example,

    It may be better to put all of the error interrupts at a high (or low, depending on your thinking) priority and the RX/TX data interrupts at a low (or high again depending on your thinking) interrupt.   Putting the data and the error interrupts on the same level kind of defeats the purpose of having the 2 levels but maybe it would make the example too complex if it used both.

    Anyway thanks for the feedback here - I'll enter a CQ ticket on the issues you point out so they get queued up to be addressed in a future release.

    Best Regards,

    Anthony

    EDIT: BTW here is the CQ#: SDOCM00118047

  • 0 in reply to Anthony F. Seely
    Guru 15740 points

    My doubts were on the right combination of the VIM tabs and the MIBSPI 1->5  tabs (screenprint below):

    I couldn't make out after reading the text and looking at the picture in the help, if the VIM Channel tabs and MIPSPI(x) Global tabs need to be set or not.

    I have the example working (MIBSPI 1 -> 5 are sending and receiving as expected) by not selecting anything on the MIBSPI(x) Global tabs, and enabling the MIBSPI interrupts on VIM Channel (0->63) tabs,
    but I'm not sure if that's the right way.

  • 0 in reply to Anthony F. Seely
    Guru 15175 points
    I will try to implement the same code with RM57 to perform the same tests; previously we tried to use the SPI module, with a memory 25LC256 but the SPI module(RM46), did not work as expected.