Hello All,
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Hello All,
John,
Yes - the CPU supports HIVECS, but the Hercules memory map has evolved from the original memory map of the TMS470R1x which was ARM7 based. And at that time it made a lot of sense to put the critical system registers like the hardware interrupt vector up at 0xFFFFFFxx because you could reach this with a LDR using PC offset by -#imm12 from the vector table, so you could read the hardware generated index without loading any pointers or using any registers. Big advantage at the time. unfortunately it conflicts w. HIVECS now.
The system software interrupts are documented in the TRM - they're part of the system module.
Pasting image of one of the SSIR registers from the RM57L TRM but they should be on all the devices.
These go to VIM like any other interrupt - hence the slight differences I mentioned above w. regard to masking and the possibility that you may need to setup for nesting if you call from IRQ mode. But otherwise - they're similar to SWI. You can even pass a code like you do on a SWI through the SSIR register.
Ok all this said - i should say that I believe the bootloader from QJ is designed to have a fixed branch at the SWI vector - into the next sector of flash where you could put your own code. A fixed branch also doesn't use registers, so it's good unless you cannot execute from flash when you're making the SWI call for some reason. So if you can use that mechanism, it's probably worth looking at first.
Last, there is an ability to swap the addresses of FLASH and RAM in the device memory map but it's kind of a drastic thing to do and you may run into issues with the flash APIs - not sure. More of an FYI rather than a recommendation. Register for this is also in the system module (BMMCR1) and you need to follow it with a CPU reset in order to make the swap take effect.
Anthony,
Thanks for the quick response.
I agree that I should just fix the branch from QJ's original code. That is certainly the easiest right now.
I think what has been done vs. the early days of ARM is absolutely fantastic; but the one offs such as not being able to use the HIVECS now; hmmm - it still isn't bad but would be nice if the original ARM docs could be annotated - but maybe that is impossible due to all the variants.
The infocenter site ARM has is a God-send though - compared to what we were working with in circa 1997.
And, thanks for letting me know about the CPU reset being necessary after that swap - I wasn't aware of that; that's an important point as you've pointed out.
I will take a look at this and report back.
Again, thank you for the fast response,
John W.