Hello,
We have found a mistake in the PLL configuration in our code. Basically we are configuring PLLCTL1, PLLCTL2, etc to run at 180Mhz, (we are using TMS570LS3137)
Because of an error in code after that we have the code:
-----------------------------------------------
/* Workaround for FMZPLL#17 errata */
systemREG1_Const->PLLCTL1 = 0x41036300U;
systemREG1_Const->PLLCTL1 = config->Pllctl1_u32;
/* Clearing the Slip Bit */
systemREG1_Const->GBLSTAT = 0x300;
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config->Pllctl1_u32 is equal to 0x400058600 (this is the also the value in PLLCTL1 before running the previous code.
The problem is that we have already created the release so changing this code would mean several days/weeks of testing, documentation updates, etc, so if it is possible we would prefer to not change it.
1) We understand that this errata, FMZPLL#17 does not apply to TMSLS3137 but only to TMSLS20... is that correct?
2) Would this erroneous code produce any PLL slip?
3) Also would the PLL lock still be valid?
4) Any other reaction, etc to consider because of this error?
We can not see any problem during our tests, but we would like to be sure that this is no problem.
Regards,
Francis.
