What's wrong with that HW-DMA control packet?

The SW-triggered DMA channel 0 is working fine.
The HW-triggered DMA channel 1 is not working. 
SCI is working (tested in polling mode).
HW is TMS570 on LAUCHPAD.

void dmaInit(uint32 bufAddr, uint32 nShort)
{
	dmaREG->GCTRL = 0; // SW reset during configuration (HALCoGen-generated code is enabling dma here, the Reference Manual is warning to do so)
	dmaREG->PAR[0] = dmaREG->PAR[1] = 0xFFFFFFFF; // assign to Port B (no choice)
	// dmaREG->DMAPCR = 0x0A; // enable parity <======= ToDo

	// dma channel 0 compresses (in-place) the HTU-delivered data (uint32) to 16-bit-aligned array of uint16
	dmaRAMREG->PCP[0].ISADDR = bufAddr +2; // MCU is big endian, copy from little end
	dmaRAMREG->PCP[0].IDADDR = bufAddr; // copy in-place
	dmaRAMREG->PCP[0].ITCOUNT = (1<<16) // one frame
                                  + nShort; // of nShort short ints
	dmaRAMREG->PCP[0].CHCTRL  = (0<<16) // not a chain
                                  + (1<<14) // src element size 16 bit (short)
                                  + (3<<12) // dst element size 64 bit
                                  + (0<< 8) // TTYPE = HW request per frame (ignored for SW requests)
                                  + (3<< 3) // src addr mode "indexed" (meaning non-default increments)
                                  + (1<< 1) // dst addr mode "post-increment" (by element size, 8 byte)
                                  +  0;     // AIM = 0, no auto initiation
	dmaRAMREG->PCP[0].EIOFF =   (0<<16) // no non-default dst-addr element increment
                                  +  4;     // src-addr element increment
	dmaRAMREG->PCP[0].FIOFF =   (0<<16) // no non-default dst-addr frame increment
                                  +  0;     // src-addr frame increment (never mind, frame count is 1)

	// dma channel 1 transfers telegram to SCILIN's TD
	dmaREG->DREQASI[0]       =  29<<16; // assign HW request channel 29 (SCILIN TD ready) to channel 1
	// sciInit() will execute scilinREG->SETINT = 1<<16; // DMA requests on TD empty
	dmaRAMREG->PCP[1].ISADDR = bufAddr;
	dmaRAMREG->PCP[1].IDADDR = (uint32)&(scilinREG->TD);
	dmaRAMREG->PCP[1].ITCOUNT = (2*nShort<<16)// 2*nShort frames
                                  +  1;     // of 1 element (byte)
	dmaRAMREG->PCP[1].CHCTRL  = (0<<16) // no chain
                                  + (0<<14) // src element size 8 bit
                                  + (0<<12) // dst element size 8 bit
                                  + (0<< 8) // TTYPE = HW request per frame, not per buffer
                                  + (1<< 3) // src addr mode "post-increment" (by 1 element)
                                  + (0<< 1) // dst addr mode "const" (not incrementing)
                                  +  0;     // AIM = 0, no auto initiation after last frame
	dmaRAMREG->PCP[1].EIOFF = 0; // no non-default increments
	dmaRAMREG->PCP[1].FIOFF = 0; // no non-default increments

	dmaREG->GCTRL |= 0x00010000; // enable all this
}