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DCAN ECC uncorrectable error after initialization

Piotr Roszak
Intellectual 530 points
Other Parts Discussed in Thread: TMS570LC4357, HALCOGEN

Hello,

I am using TMS570LC4357 and have a problem with 'DCAN1 - ECC uncorrectable error notification' in ESM.

DCAN RAM is initialized as described in SPNU563 (27.4.1 DCAN RAM Initialization Through Hardware) using _memInit_ function generated by Halcogen.

Then I simply configure mailboxes using standard API and this error occurs.

I tried to initialize CAN RAM manually - by accordingly setting PMD bits (activating SECDEC) in DCAN CTL register and then writing 0's to the message objects memory (with 64bit words) - but still the same error.

Is something wrong in this initialization?

Piotr

  • 0
    TI__Genius 14900 points
    Piotr,
    Did you enable the RAM ECC prior to clearing? Section 27.15 contains a note
    During RAM initialization, no ECC check will be done, but if the PMD bit is set, the ECC bits will be generated.

    The PMD bit is located in CAN Control Register, bits 13:10.

    Best Regards,
    Kevin Lavery
  • 0 in reply to Kevin Lavery
    Intellectual 530 points

    Yes, I enabled ECC before writing 0's.

  • 0 in reply to Piotr Roszak
    TI__Genius 14900 points
    Piotr,
    I have initialized the CAN ECC in the following steps.
    // enable peripheral memory select for CAN1-4 RAM
    peripheral_Memory_PowerDown_Clr(pcrREG1, PCS12);
    peripheral_Memory_PowerDown_Clr(pcrREG1, PCS13);
    peripheral_Memory_PowerDown_Clr(pcrREG1, PCS14);
    peripheral_Memory_PowerDown_Clr(pcrREG1, PCS15);
    // enable peripheral select for CAN1-4
    peripheral_Frame_PowerDown_Clr(pcrREG2, PS7, (QUADRANT0 | QUADRANT1 | QUADRANT2 | QUADRANT3));
    peripheral_Frame_PowerDown_Clr(pcrREG2, PS8, (QUADRANT0 | QUADRANT1 | QUADRANT2 | QUADRANT3));

    // enable ECC within CAN
    canREG1->CTL = 0x2800;
    canREG2->CTL = 0x2800;
    canREG3->CTL = 0x2800;
    canREG4->CTL = 0x2800;

    // initialize CAN memories
    systemREG1->MINITGCR = 0xA;
    systemREG1->MSINENA = 0x100460;
    // wait for initialization to complete
    while((systemREG1->MSTCGSTAT & 0x100) == 0)
    {}
    // enable CAN ECC RAM so that ECC can be verified
    canREG1->ECCDIAG = 0x5;
    canREG2->ECCDIAG = 0x5;
    canREG3->ECCDIAG = 0x5;
    canREG4->ECCDIAG = 0x5;
    while(1)
    {}

    Best Regards,
    Kevin Lavery
  • 0 in reply to Kevin Lavery
    Intellectual 530 points

    Kevin,

    Thank you. It solved my problem.

    Best regards,
    Piotr

  • 0 in reply to Piotr Roszak
    TI__Genius 14900 points

    Piotr,

         Glad that worked.

    Best Regards,

    Kevin Lavery