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TMS570LC4357 MibSPI transfert group maximum size

Other Parts Discussed in Thread: TMS570LC4357

Hi all

We are trying to use MibSPI1 bus of TMS570LC4357 to read and write an entire page of SPI e2prom

having a page size of 256 bytes. Consequently, we need to use a group made of 130 buffers (16 bits each)

We have used SPI1 bus having a 256 buffers Tx/Rx RAM, but we face some problems and have some

questions :

1/ We want ot use a group made of 130 buffers (2 for command word and 24 bits address +  128 buffers for the 256 bytes of data)

but we are not sure that LPEND field of LTGPEND register accepts an end address greater than 127 (but an 8 bits value

in this field is still writable).

2/ We have defined three groups, in following order

- group 0, starting at address 0 : one buffer (for 8 bits sendings such as write enable commad)

- group 1, starting at address 1 : one buffer (for 16 bits sendings such as read status reg of e2prom)

- group 2, starting at address 2 : 130 buffers (for read/write commadn+ 24 bits address + 256 bytes)

When trying to send group 2, the transfert works only up to buffer 127 (so the end of "non extended" RAM)

and transfert never ends

So our questions are

1/ Can we program and use a single group of more than 128 buffers ?

2/ Can we program a single buffer even smaller than 128 buffers but lying between end of normal mode buffer (addresse 127) and beginnig og extended buffer (address 128 and greater). If yes, which value do we have to program in LPEND field of LTGPEND register when end of buffer is greater than 127 ?

Hoping you can help us

Regards

Sylvain BALSSA

  • Hi Sylvain,
    Can you please confirm that in the MIBSPIE register you have enable for extended buffer mode? You need to write 0xA to the EXTENDED_BUF_ENA field to enable extending the buffer range to 256 buffers.
  • Hi Charles

    I forgot to say it but yes we have set the MibSPI1 in extended mode by writing 0xA in EXTEND_BUF_ENA field

    In CCS6, the content displayed for MIBSPIE register of mibspi1 is 0x00000A01 once the soft initialisation is done

    Thanks

  • Hi Charles

    By chance we have found why it didn't work with buffers located above number 127.

    We have initialised the TGxCTRL registers of unsed groups with a PSTARTx address set to 127

    (TGxCTRL = 0x00007F00) but even  if these groups are not enabled (GTENA = 0) the

    PSTART field seems "analysed" by mibspi sequencer.

    So now, we have set TgxCTRL value to 0x00000000 for all unused groups and the group

    made of more than 128 buffers works fine !

    The remaining point is still to be sure that documentation concerning start and end addresses

    of groups for SPI1 (PSTARTx field in TGxCTRL registers, and LPEND field in LTGPEN register)

    can be defined on 8 bits and not only on 7 bits, in order to make buffers from 128 to 255 usable

    by any transfert group

    Best regards

    Sylvain

  • Hi Sylvain,

    The LPEND in the LTGPEND should be 8-bit from 15:8. It is a mistake to state that it is only 7 bits because it depends which MibSPI you are using. Same for the PSTART in the TGxCTRL registers. For MibSPI2,3,4,5 the LPEND/PSTART is indeed 7 bits only. However, for MibSPI1 it is 8 bits. I will submit a documentation feedback to add clarification.