TMS570LS1227 reset timing

Richard,

Good point. I can't answer the question either.

The glitch filter time though is something different. That parameter (tf(nRST)) has to do with an externally generate nRST signal being seen by the device.

There is a little additional information on startup time in Table 6-3. Power-Up Phases. I think it says that the starting point for this 3497 oscillator cycle number is when power on reset is released (assuming this comes after the supply voltages are within spec).

But the oscillator startup time has to be accounted for here to turn 'oscillator cycles' into time. And we don't really specify a minimum amplitude on the oscillator. While the inverter that is in the feedback loop of the osc doesn't have hysteresis I believe there is a separate inverter that has some hysterisis which converts the oscin into a 'square wave' type clock for the device. So there's probably some minimum amplitude needed but it isn't specified. Therefore to be conservative you probably should use the amount of time it takes for your oscillator to reach full peak-peak amplitude and then add the 3497 cycles of that osc to this time in order to set some sort of bounds if you need one.

Bob Crosby thank you for catching my error...

Richard - I read your glitch filter question incorrectly - got it confused as being all one question.

Yes you are right the maximum time from the ASSERTION of power on reset (low) to RESET (low) is the glitch filter time.
(Again I misread and took this question to be about the deassertion)

Thanks Anthony. Would it be possible to get somebody to add the information to the datasheet? As one of my colleagues pointed out, nRST might never go high after nPORRST is released and still meet the chip specification since no maximum time is given in the datasheet!

Regards,
Richard

Thanks Anthony. I will mark your post above as a verified answer.